Jobs
Sr. Field Applications Engineer, CA for Real Intent at Sunnyvale, or San Diego, CA
Sr. R&D Engineer for Real Intent at Sunnyvale, CA
SW Developer Custom Placement P&R for EDA Careers at San Jose, CA
Applications Tech Support- NOT just EDA for EDA Careers at San Jose, CA
FAE EMULATION PROTOTYPING for EDA Careers at AUSTIN, TX
***JAVA CAD/SW Engineer*** for EDA Careers at San Jose, CA

Tech & White Papers
The integrated EDA tool suite from Tanner EDA, Incentia and Aldec is helping a growing ASIC design house keep design costs down and design efficiency high - with no …
Computation of Capacitance, Inductance, and Potential Distribution of Integrated-Circuit Interconnects for Unshielded Four Conductors with Three Levels Systems, Comsol Featured Paper by S.M. Musa, M.N.O. Sadiku & J.D. Oliver In this paper an attempt has been made to design and analyze integrated circuit interconnects for unshielded …
Numerical Calculation of the Dynamic Behavior of Asynchronous Motors with COMSOL Multiphysics, Comsol Featured Paper by J. Güdelhöfer, R. Gottkehaskamp & A. Hartmann This paper shows how a time-dependent and non-linear simulation of the dynamic …
Upcoming Events
DesignCon 2015 at Santa Clara Convention Center Santa Clara CA - Jan 27 - 30, 2015
Pan Pacific Microelectronics Symposium at Kauai Island HI - Feb 2 - 5, 2015
SEMICON Korea 2015 at COEX Seoul Korea (South) - Feb 4 - 6, 2015
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
#I’mEDAToolUser: Pay or Be Paid
Peggy AycinenaIP Showcase
by Peggy Aycinena
eSilicon: Kick the IP before you buy
More Editorial  
Latest Blog Posts
Stan HanelAldec Design and Verification
by Stan Hanel
Scaling the “Internet of Things”
Tom Anderson, VP of MarketingThe Breker Trekker
by Tom Anderson, VP of Marketing
What to Run on Day One in the Bring-Up Lab
Colin WallsEmbedded Software
by Colin Walls
What is “real time”?
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Books For Sale
Starter's Guide to Verilog 2001 , by Michael D. Ciletti.
FAE EMULATION PROTOTYPING



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