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Tech & White Papers
The integrated EDA tool suite from Tanner EDA, Incentia and Aldec is helping a growing ASIC design house keep design costs down and design efficiency high - with no …
Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification, Atrenta, Inc. Multiple, independent clocks have become a fact of life on SoCs and other complex ASICs. In extreme cases, such as in large communications processors, clock domains may …
Improve Reliability with Accurate Voltage-Aware DRC, Mentor Graphics Power challenges in today's IC designs create a significant increase in verification complexity. Critical design rule checking of variable spacing rules for …
Upcoming Events
EMC 2014 at Raleigh Convention Cente NC - Aug 3 - 8, 2014
West Penn Expo and Tech Forum at DoubleTree Monroeville 101 Mall Plaza Blvd. Monroeville PA - Aug 14, 2014
Capital Expo and Tech Forum at Johns Hopkins University/Applied Physics Lab 11100 Johns Hopkins Rd. Laurel MD - Sep 9, 2014
SMTA International 2014 at Donald Stephens Convention Center Rosemont IL - Sep 28 - 2, 2014
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Rhines: EDAC’s Numbers as The World Turns
More Editorial  
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