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Tech & White Papers
The integrated EDA tool suite from Tanner EDA, Incentia and Aldec is helping a growing ASIC design house keep design costs down and design efficiency high - with no …
Mastering the Magic of Multi-Patterning, Mentor Graphics Multi-patterning technology was introduced at the 20 nm node to overcome lithographic limitations in current IC manufacturing processes. While …
Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification, Atrenta, Inc. Multiple, independent clocks have become a fact of life on SoCs and other complex ASICs. In extreme cases, such as in large communications processors, clock domains may …
Upcoming Events
TowerJazz Global Symposium – September 18 – Amsterdam at NH Amsterdam Centre, Stadhouderskade 7, Amsterdam Netherlands - Sep 18, 2014
CDNLive Austin - Registration Now Open! at Hilton Austin TX - Sep 18, 2014
IPC India 2014 at electronica India & productronica India 2014 at Bangalore International Exhibition Centre (BIEC) Bangalore India - Sep 23 - 25, 2014
DVCon India – September 25-26 – Bangalore, India at Hotel Park Plaza 90-4 Marathahalli/Outer Ring Road, Bangalore India - Sep 25 - 26, 2014
Editorial
Peggy AycinenaIP Showcase
by Peggy Aycinena
9/11: Jim Hogan and My father’s shoes
More Editorial  
Latest Blog Posts
Tom Anderson, VP of MarketingThe Breker Trekker
by Tom Anderson, VP of Marketing
A Concise History of the Breker Product Line
Colin WallsEmbedded Software
by Colin Walls
Small or fast?
Jin ZhangDecoding Formal
by Jin Zhang
Using Formal for Functional Coverage
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