Field Applications Engineer for Real Intent at Sunnyvale, CA

Strategic Account Manager for Atrenta at San Jose, CA

Emulation Applications Engineer for Mentor Graphics at Fremont, CA

Sr. Software Engineer for DCG Systems at Fremont, CA

Sr. Field Applications Engineer (San Jose, CA & Austin, TX) for Atrenta at San Jose, CA

Lead Field Applications Engineers (Shanghai & ShenZen, China) for Atrenta at San Jose, CA

The EDA & MCAD/MCAE Almanac: Q2 2011
Latest post : May 20, 2013, 4:59:pm
EDA User News and Reviews

PLDA - The PLDA SoMZ-7045 (based on the Xilinx Zynq AP SoC) combines the flexibility and ease …

CAST - Implements a Real Time Transport Protocol (RTP) hardware stack that encapsulates …

Arasan Chip Systems, Inc. - The Arasan USB 2.0 PHY IP core is a transceiver compliant with the …

Posedge Inc - The Posedge Quad Serial Flash Controller (PE-SFC) IP provides an interface to …

Digital Core Design - DμART, the newest IP Core mastered by Digital Core Design, is one of …

 IP Search

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Fundamentals of Floor Planning A Complex SoC, Kilopass Floor planning is among the most crucial steps in the design of a complex system-on-a-chip (SoC), as it represents the tradeoffs between marketing objectives …

HES-7 ASIC Prototyping, Aldec Co-authored by: Slawek Grabowski and Zibi Zalewski, Aldec, Inc. & Kirk Saban, Xilinx, Inc. This paper highlights possibilities of ASIC …

AO@SW with Vrala: Simulations and Tests, Comsol Featured Paper by C. Del Vecchio, G. Agapito, L. Carbonaro, F. Marignetti, E. De Santis & Y. Coia VRALA is the ideal candidate as an Adaptive Optics actuator …

Michigan Expo & Tech Forum - May 23, 2013 at To Be Decided - May 23, 2013

DAC 2013 at Austin Convention Center Austin TX - Jun 2 - 6, 2013

e Golden Reference Guide, by Doulos.

Application-Specific Integrated Circuits (ASICs... the book), by Michael John Sebastian Smith.

LabVIEW Graphical Programming - Preface, by Gary W. Johnson, Richard Jennings.

Hard IP, an introduction to increasing ROI for VLSI Chip designs, by Peter Rohr.