Jobs
Sr. Field Applications Engineer for Real Intent at Sunnyvale, CA
FAE POWER EXPERT RTL for EDA Careers at AUSTIN, CA
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Sr Software Engineer - Integrator Team for Xilinx at San Jose, CA
Sr. R&D Engineer for Real Intent at Sunnyvale, CA
Forum Topics
The DATE 2014 conference and exhibition in Dresden attracted
Latest post : April 7, 2014, 10:36:pm
EDA User News and Reviews
Altium - Opening A New Umbrella
EDA User News and Reviews

Tech & White Papers
SpyGlass Flow for XILINX FPGA, Atrenta SpyGlass Lint and CDC are critical analysis tools for RTL designs that identify chip killer problems and shorten design cycle time. This document highlights the issues …
Analysis of Random Resistive Faults and ATPG Effectiveness at RTL, Atrenta Traditional netlist-based DFT analysis runs into design rule violations during scan insertion in synthesis and needs RTL designers to modify …
Congestion Mitigation During RTL Development, Atrenta, Inc. Early physical design closure is critical for successful SoC delivery. Routing congestion is one of the key aspects of physical design closure. In …
Upcoming Events
Decoding Formal Club for Formal Verification Enthusiasts at Computer History Museum Mountain View CA - Apr 21, 2014
Atlanta Expo and Tech Forum at Gwinnett Civic Center 6400 Sugarloaf Parkway Duluth GA - May 7, 2014
International Conference on Soldering and Reliability at United States - May 13 - 15, 2014
SEMICON Russia 2014 at Moscow Russia - May 14 - 15, 2014
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
EDA Sales: Debunking the narrative
More Editorial  
Latest Blog Posts
Colin WallsEmbedded Software
by Colin Walls
Parlez vous Fortran?
Tom Anderson, VP of MarketingThe Breker Trekker
by Tom Anderson, VP of Marketing
Ruminating about Accelerating, Emulating, and Prototyping
Ankit GopaniASIC with Ankit
by Ankit Gopani
Class – The Classic Feature – Part II
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