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What's New on EDACafe
Icahn Issues Statement Regarding Upcoming Annual Meeting of Shareholders of Mentor Graphics Corporation
HP Announces New Mobile and Cloud-based Large-format Printing Solutions for Design Professionals
Trojan Defense and Silvaco Announce Collaboration for Development of Trojan Defense's Carnyx™ …
Murrietta signs D.B. Management Group
Prototron Circuits Earns Environmental Award
Atrenta’s unified platform
Joe Costello: Orb, Oasys, Epicenter
Cadence Seminar: Reduce SoC Development Time with Cadence IP and VIP (May 22 in Boston and May 24 in Ottawa)
AMIQ Has a New Logo
EVE Unveils 10-Gigabit Ethernet Validation Platform
EVE Adds New Applications for Leading SoC Emulation Platform Environment
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Important Notices
AMD, Broadcom, NVidia speak on Design & IP Management @ DAC, June 4, San Francisco
John Cooley's DAC TroubleMaker's Panel on June 4 in San Francisco
The Future of the IP Industry is in Your Hands: Register Now for Semico's IP Conference
Video Invitation to "Milestones to Building a Successful Technology Software Company", May 31
IPC Conference on Flexible Circuits (June 12-14)
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Audio Interviews
"SEMI-THERM Tackles Semiconductor Thermal Challenges", Herman Chu, Gen. Chair
IEEE Semiconductor Thermal Management and Measurement Symposium
"Keynote: 3D Device Technologies - Opportunities and Challenges", Dr. Jong Shik Yoon, Samsung
Common Platform Technology Forum 2012
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Mark Gilbert
EDA Careers Corner & More
A Must Read: The Most Common Catastrophic Interviewing Mistakes Made By Companies…
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Dr. Russ Henke
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Morning at the Oasys
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Tutorials
Clock Domain Crossing (CDC) Design Techniques
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Infrared detector arrays for thermal imaging (Tutorial "Infrared Detectors")
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Verification IP, Synopsys Inc.
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How to verify ASD Models using the ASD:Suite, Verum Software B.V.
The following video introduces the alternatives to verify ASD:Suite Models using the ASD:Suite Release 3 and provides a basic overview of the user interface and of the …
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Online Events
Mentor Graphics: Learn How to Maximize Your Ability to Debug Your Testbench (May 24)
Eliminating Bottlenecks in MEMS-IC Co-Design: SoftMEMS & Tanner EDA Free Webinar
Cadence: Industry Leaders Unveil Shared Vision for 20nm (On Demand)
DataLight: Making the Move to eMMC (On Demand)
Microsemi: System Management for High Availability Systems (On-Demand)
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Common Platform Tech. Forum 2012 Online: Keynotes, Exec. Panel, Tech. Webinars
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Embedded, IP & SoC News
Teseq Holding AG to Acquire IFI, Increasing Its Presence in the RF Amplifier Market
Samsung Now Producing Highest Density Mobile LPDDR2 Memory Using 20nm-class Technology – an …
ASSET’s Two New ScanWorks Controller Kits Tap into High-Speed PCI Express Bus
GigOptix, Inc. Samples Linear Quad Driver for 400G Applications
Intilop's Nano TOE performs Full TCP/IP Stack processing in yet another record breaking 76 ns!
TowerJazz Presents First Quarter 2012 Financial Results
Fairchild Semiconductor’s Enhanced Reset Timers Give Mobile Device Users a Simple Reset Solution …
Texas Instruments low-power FPD-Link serializer offers industry's highest resolution for tablets
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Corporate Newsletters
AMIQ: Come and learn about our code development and analysis tools in Booth #1804 at DAC
IPC Outlook: What are the Pros and Cons of Cleaning No-Clean?
Apache Customers Present at DAC 2012, Booth #1813
SoCIP Newsletter, Spring 2012
Synopsys Insight: Issue 1, Mar 2012 - Synopsys and Samsung Address 20nm Gigascale ICs, Fast Track to 3D-IC Testing, and Next Generation Verification IP
Cadence News - April 2012: Driving the Cloud Revolution with Cadence VIP, Taming Custom/Analog 20nm …
Apache Design April 2012: RTL Power Model (RPM) Wins DesignVision Award
Q2-2012 - Aldec™ Design and Verification Newsletter
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Tech & White Papers
Randomization and Functional Coverage in VHDL, Aldec
Modern digital designs reach the scale of complete systems and require support of Constrained Random Test and Functional Coverage in verification. Although VHDL …
Methods for Configurable Hardware Design, Kilopass
While adding post silicon production configurability has ample precedence with the introduction of FPGA devices in the late 1980’s, it is a …
Expect faster adoption of IDEs in hardware design and verification, AMIQ
Integrated Development Environments have been popular in the software world for many years. While the first platforms were dedicated to a single language, modern …
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Latest IPs
Creonic - The IEEE 802.11n/ac standards require high data rates of up to 600 Mbit/s for …
HDL Design House - The PCI Express SerDes PHY is a hard IP core that implements the physical …
Creonic - Convolutional codes are widely adopted in wireless communication systems for forward …
HDL Design House - The HIP3510 DSI Peripheral Controller IP is a highly configurable, …
Creonic - DVB-C2 (Digital Video Broadcast - Cable 2nd Generation) is an ETSI standard of the …
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DAC 2012: Wicked Wednesday in San Francisco
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New 3rd Generation Debug Platform, Verdi³™, Mark Milligan, SpringSoft
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Oski Technology
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