Field Applications Engineer for Real Intent at Sunnyvale, CA

Strategic Account Manager for Atrenta at San Jose, CA

VP Engineering Front End for EDA Careers at San Jose, CA

Sr. Field Applications Engineer (San Jose, CA & Austin, TX) for Atrenta at San Jose, CA

AE's BACK END AUSTIN, SOCAL Bay Area for EDA Careers at San Jose, CA

AE's P&R San Diego and Austin for EDA Careers at San Jose, CA

Supplements Usage in India
Latest post : June 7, 2013, 1:00:am
Verilog Discussion Board

CAST - The BA2x-AXI-PP provides the essential IP cores and infrastructure software needed for …

True Circuits - TSMC CLN28HPL 28nm Multi Phase DLL - 440MHz-2200MHz

PLDA - The PLDA SoMZ-7045 (based on the Xilinx Zynq AP SoC) combines the flexibility and ease …

Posedge Inc - The Posedge 802.11 ac WLAN MAC is a low-cost, low-power, high-performance, and a …

Vitesse Semiconductor - 10/100/1000BASE-T Copper PHY 2-port hard macro IP Core for TSMC 65GP …

 IP Search

Find detailed information about thousands of commercially available IP blocks from more than 230 suppliers.

HES-7 ASIC Prototyping, Aldec Co-authored by: Slawek Grabowski and Zibi Zalewski, Aldec, Inc. & Kirk Saban, Xilinx, Inc. This paper highlights possibilities of ASIC …

JasperGold Apps - Interoperable Application-Specific Solutions for Formal Verification Throughout the Design Flow, Jasper Design Automation This white paper describes JasperGold® Apps, a family of interoperable formal verification solutions.

Design Optimization of Waveguide Applicator for Microwave Hyperthermia Cancer Treatment, Comsol Featured Paper by P. Kumar , S. Kalra & A. Marwaha The optimized design of a waveguide applicator has been proposed for superficial microwave hyperthermia using …

Atrenta Seminar: Making RTL Signoff Real at Dan Accadia Hotel Herzliya Israel - Jun 19, 2013

Upper Midwest Expo & Tech Forum - June 20, 2013 at Embassy Suites Bloomington 2800 American Blvd. West Bloomington MN - Jun 20, 2013

Charge Pump Circuit Design - Chapter 1, by Feng & Tapan.

Advanced Verification Topics - Table of Contents, by Bishnupriya Bhattacharya and contributors.

Logic Design for Array-Based Circuits, by Donnamaie E. White.

Hard IP, an introduction to increasing ROI for VLSI Chip designs, by Peter Rohr.