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Trojan Defense and Silvaco Announce Collaboration for Development of Trojan Defense's Carnyx™ Ionizing Radiation and Neutron Detector
Murrietta signs D.B. Management Group
Prototron Circuits Earns Environmental Award
Atrenta’s unified platform
Joe Costello: Orb, Oasys, Epicenter
Cadence Seminar: Reduce SoC Development Time with Cadence IP and VIP (May 22 in Boston and May 24 in Ottawa)
AMIQ Has a New Logo
EVE Unveils 10-Gigabit Ethernet Validation Platform
EVE Adds New Applications for Leading SoC Emulation Platform Environment
Carbon Design Systems Unveils Off-the-Shelf Performance Analysis for ARM Cortex-A Processors
Vestel Electronics Launches Advanced Set-Top-Box Using Mentor Graphics Inflexion User Interface …
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Important Notices
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AMD, Broadcom, NVidia speak on Design & IP Management @ DAC, June 4, San Francisco
John Cooley's DAC TroubleMaker's Panel on June 4 in San Francisco
The Future of the IP Industry is in Your Hands: Register Now for Semico's IP Conference
Video Invitation to "Milestones to Building a Successful Technology Software Company", May 31
Call for Papers ASP-DAC 2013
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 Audio Interviews
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 Editorial
Mark Gilbert: President EDA-Careers Mark Gilbert
EDA Careers Corner & More
A Must Read: The Most Common Catastrophic Interviewing Mistakes Made By Companies…
Archived Careers Corner
Dr. Russ Henke Dr. Russ Henke
EDA & IP Commentary
Morning at the Oasys
Archived Commentary
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 Tutorials
FPGA Floorplanning
Clock Domain Crossing (CDC) Design Techniques
Actel Quick Start Guide for Libero IDE v8.0
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 Presentations
Verification IP, Synopsys Inc. VIP
How to check and fix conflicts using the ASD:Suite, Verum Software B.V. The following video presents the ways in which you can identify specification inconsistencies, also known as conflicts, in your ASD:Suite Model and ways how to fix the …
Simbeor Screen-Casts, Simberian Inc. S-parameters quality assurance and macro-modeling automation with Touchstone Analyzer tool in Simbeor
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Aldec -Taking Verification to the next level

 
Online Events
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Mentor Graphics: Advanced PCB Design Software - See it in action (May 24)
Mentor Graphics: Learn How to Maximize Your Ability to Debug Your Testbench (May 24)
Eliminating Bottlenecks in MEMS-IC Co-Design: SoftMEMS & Tanner EDA Free Webinar
Cadence: Industry Leaders Unveil Shared Vision for 20nm (On Demand)
DataLight: Making the Move to eMMC (On Demand)
Microsemi: System Management for High Availability Systems (On-Demand)
Enjoy Virtual Common Platform Tech. Forum 2012 Online: Keynotes, Exec. Panel, Tech. Webinars
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Embedded, IP & SoC News
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Teseq Holding AG to Acquire IFI, Increasing Its Presence in the RF Amplifier Market
Samsung Now Producing Highest Density Mobile LPDDR2 Memory Using 20nm-class Technology – an …
ASSET’s Two New ScanWorks Controller Kits Tap into High-Speed PCI Express Bus
GigOptix, Inc. Samples Linear Quad Driver for 400G Applications
Intilop's Nano TOE performs Full TCP/IP Stack processing in yet another record breaking 76 ns!
TowerJazz Presents First Quarter 2012 Financial Results
Fairchild Semiconductor’s Enhanced Reset Timers Give Mobile Device Users a Simple Reset Solution …
Texas Instruments low-power FPD-Link serializer offers industry's highest resolution for tablets
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Corporate Newsletters
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AMIQ: Come and learn about our code development and analysis tools in Booth #1804 at DAC
IPC Outlook: What are the Pros and Cons of Cleaning No-Clean?
Apache Customers Present at DAC 2012, Booth #1813
SoCIP Newsletter, Spring 2012
Synopsys Insight: Issue 1, Mar 2012 - Synopsys and Samsung Address 20nm Gigascale ICs, Fast Track to 3D-IC Testing, and Next Generation Verification IP
Cadence News - April 2012: Driving the Cloud Revolution with Cadence VIP, Taming Custom/Analog 20nm …
Apache Design April 2012: RTL Power Model (RPM) Wins DesignVision Award
Q2-2012 - Aldec™ Design and Verification Newsletter
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 Tech & White Papers
Methods for Configurable Hardware Design, Kilopass While adding post silicon production configurability has ample precedence with the introduction of FPGA devices in the late 1980’s, it is a …
SystemVerilog Made Easy: A Perl Interface to a Full IEEE 1800 Compliant Parser, Verific Design AUtomation Since the adoption of hardware description languages (HDLs) as the methodology of choice for digital design in the early 1990s, an abundance of …
Solving Engineering File Transfer Problems: Two Different Days in the Life of an Engineer, OpenText connectivity Solutions Group Optimize the Engineering Design Workflow and Send your Large Files Faster...
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 Latest IPs
Creonic - The IEEE 802.11n/ac standards require high data rates of up to 600 Mbit/s for …
HDL Design House - The PCI Express SerDes PHY is a hard IP core that implements the physical …
Creonic - Convolutional codes are widely adopted in wireless communication systems for forward …
HDL Design House - The HIP3510 DSI Peripheral Controller IP is a highly configurable, …
Creonic - DVB-C2 (Digital Video Broadcast - Cable 2nd Generation) is an ETSI standard of the …
 
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 Upcoming Events
The Top Five Challenges to Effective Cost Controls at The Carlton Hotel. 88 Madison Avenue (between 28th & 29th Street). NY - May 24, 2012
EDA Consortium 2012 Spring Members Meeting at Silicon Valley Bank 3005 Tasman Drive Santa Clara CA - May 31, 2012
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 Latest Blog Posts
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DAC 2012: Wicked Wednesday in San Francisco
Ed LeeWhat's PR got to do with it?
by Ed Lee
Atrenta’s unified platform
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 Jobs
Technical Marketing Manager – RTL Analysis and CDC Verification for Atrenta at San Jose, CA
AMS Senior Developer for EDA Careers at San Jose, CA
Principal Member of Technical Staff, Graphical User Interface (GUI) for EDA Careers at San Jose, CA
Technical R&D Manager for SpringSoft USA, Inc. at San Jose, CA
Field AE’s Physical Domain Valley, Austin, SOCAL for EDA Careers at San Jose, CA
Sr. Technical Marketing Engineer (Power) - San Jose for Atrenta at San Jose, CA
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 Online Books
Advances in Electronic Testing: Challenges and Methodologies (Frontiers in Electronic Testing).
The Finite Element Method in Electromagnetics, by Jian-Ming Jin.
FPGAs: World Class Designs.
Problems and Solutions on Electromagneti (Major American Universities Ph.D. Qualifying Questions and Solutions).
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 Books For Sale
Advances in Electronic Testing: Challenges and Methodologies (Frontiers in Electronic Testing) .
Problems and Solutions on Electromagneti (Major American Universities Ph.D. Qualifying Questions and Solutions) .
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 Forum Topics
A Must Read: The Most Common Catastrophic Interviewing Mista
EDA User News and Reviews
latest post : May 5, 2012, 8:10:pm
Monthly EDA lunch in Portland, OR
EDA Industry
CMOS Transmission Gate
EDA Weekly
Calculus 6th ed by James Stewart
EDA Industry
INSTRUCTOR SOLUTIONS MANUAL
VHDL Discussion Board
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Jasper Design Automation
Calypto:Empowering the Next Level of Design



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