Jobs
Sr. Field Applications Engineer, CA for Real Intent at Sunnyvale, or San Diego, CA
FAE EMULATION PROTOTYPING for EDA Careers at AUSTIN, TX
Applications Tech Support- NOT just EDA for EDA Careers at San Jose, CA
***JAVA CAD/SW Engineer*** for EDA Careers at San Jose, CA
Sr. R&D Engineer for Real Intent at Sunnyvale, CA
Engineering Technology Director for Atrenta at San Jose, CA

Tech & White Papers
The integrated EDA tool suite from Tanner EDA, Incentia and Aldec is helping a growing ASIC design house keep design costs down and design efficiency high - with no …
Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification, Atrenta, Inc. Multiple, independent clocks have become a fact of life on SoCs and other complex ASICs. In extreme cases, such as in large communications processors, clock domains may …
Calibration of MHD Flow Meter using COMSOL Multiphysics, Comsol Featured Paper by S. Sahu, R. P .Bhattachryay & E. R. Kumar There is limited option for non-intrusive flow measurement of liquid metals at high …
Upcoming Events
DVCon 2015 at Double Tree San Jose CA - Mar 2 - 5, 2015
Essentials of Electronics & SMT, BGA, & BTC Design & Manufacturing at 13727 - 460th Ct SE North Bend WA - Mar 2 - 6, 2015
CST Webinar:Getting Ahead with CST PCB STUDIO at United States - Mar 5, 2015
IoT Summit 2015 at Convention Center, Santa Clara CA - Mar 5 - 6, 2015
Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon: in 12 minutes
More Editorial  
Latest Blog Posts
Tom Anderson, VP of MarketingThe Breker Trekker
by Tom Anderson, VP of Marketing
The Importance of DVCon and Why Breker Will Be There
Stan HanelAldec Design and Verification
by Stan Hanel
Xilinx Tcl Store Integrates Aldec Simulators with Vivado IDE
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