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Tech & White Papers
The integrated EDA tool suite from Tanner EDA, Incentia and Aldec is helping a growing ASIC design house keep design costs down and design efficiency high - with no …
Improve Reliability with Accurate Voltage-Aware DRC, Mentor Graphics Power challenges in today's IC designs create a significant increase in verification complexity. Critical design rule checking of variable spacing rules for …
Congestion Mitigation During RTL Development, Atrenta, Inc. Early physical design closure is critical for successful SoC delivery. Routing congestion is one of the key aspects of physical design closure. In …
Upcoming Events
Capital Expo and Tech Forum at Johns Hopkins University/Applied Physics Lab 11100 Johns Hopkins Rd. Laurel MD - Sep 9, 2014
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SMTA International 2014 at Donald Stephens Convention Center Rosemont IL - Sep 28 - 2, 2014
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Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
ShakeAlert vs. QuakeFinder: Predicting the Big One
Peggy AycinenaIP Showcase
by Peggy Aycinena
Venn Diagram: EDAC, EDA, ARM TechCon 2014
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