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11.1   A Counter

The following Verilog code models a "black box" that contains a 50 MHz clock (period 20 ns), counts from 0 to 7, resets, and then begins counting at 0 again:

`timescale 1ns/1ns // Set the units of time to be nanoseconds.
module counter; 
  reg clock; // Declare a reg data type for the clock.
  integer count; // Declare an integer data type for the count.
initial // Initialize things; this executes once at t=0.
  begin 
    clock = 0; count = 0; // Initialize signals.
    #340 ; // Finish after 340 time ticks.
  end 
/* An always statement to generate the clock; only one statement follows the always so we don't need a begin and an end. */
always  #10 clock = ~ clock; // Delay (10ns) is set to half the clock cycle.
/* An always statement to do the counting; this executes at the same time (concurrently) as the preceding always statement. */
always   begin    // Wait here until the clock goes from 1 to 0.
    @ (negedge clock);
    // Now handle the counting.
    if (count == 7)
      count = 0;
    else      count = count + 1;
    ("time = ",," count = ", count);
  end 
endmodule

Verilog keywords (reserved words that are part of the Verilog language) are shown in bold type in the code listings (but not in the text). References in this chapter such as [Verilog LRM 1.1] refer you to the IEEE Verilog LRM.

The following output is from the Cadence Verilog-XL simulator. This example includes the system input so you can see how the tool is run and when it is finished. Some of the banner information is omitted in the listing that follows to save space (we can use "quiet" mode using a '-q' flag, but then the version and other useful information is also suppressed):

> verilog counter.v
VERILOG-XL 2.2.1   Apr 17, 1996  11:48:18
    ... Banner information omitted here...
Compiling source file "counter.v"
Highest level modules:
counter
time =                   20 count =           1
time =                   40 count =           2
(... 12 lines omitted...)
time =                  300 count =           7
time =                  320 count =           0
L10 "counter.v":  at simulation time 340
223 simulation events
CPU time: 0.6 secs to compile + 0.2 secs to link + 0.0 secs in simulation
End of VERILOG-XL 2.2.1   Apr 17, 1996  11:48:20
>

Here is the output of the VeriWell simulator from the console window (future examples do not show all of the compiler output-- just the model output):

Veriwell -k VeriWell.key -l VeriWell.log -s :counter.v
... banner information omitted ....
Memory Available: 0
Entering Phase I...
Compiling source file : :counter.v
The size of this model is [1%, 1%] of the capacity of the free version
Entering Phase II...
Entering Phase III...
No errors in compilation
Top-level modules:
   counter
C1> .
time =                   20 count =           1
time =                   40 count =           2
(... 12 lines omitted...)
time =                  300 count =           7
time =                  320 count =           0
Exiting VeriWell for Macintosh at time 340
0 Errors, 0 Warnings, Memory Used: 29468
Compile time = 0.6, Load time = 0.7, Simulation time = 4.7
Normal exit
Thank you for using VeriWell for Macintosh

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