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Taking steps to prevent signal integrity (SI) problems can greatly reduce the number of SI errors that you have to fix after routing. Good prevention methods thus help minimize last-minute timing-closure panic due to SI issues such as crosstalk delay and noise. These SI issues become critical for System-on-Chip (SoC) designs at about the 150-nanometer (nm) technology node and unavoidable at 130-nm and below. SI problems can cause chip failures if ignored and lead to major timing-closure difficulties-and thus tapeout schedule delays-if left to the final stages of physical design. Using prevention methods earlier in the flow decreases the potential for these SI problems significantly. Some prevention measures are good practice for any SoC design flow, while others are more specific to SI work. This article provides an overview of SI problem prevention methods (Figure 1) and offers insight into dealing with the pervasive appearance of crosstalk delays in 90-nm designs-an overall SI profile that differs from that seen at 130-nm. Preventing SI problems in design planning Careful floorplanning and power planning are among the methods for preventing SI problems that are simply good design practice. For example, adjusting placement to minimize the distance between drivers and pins is especially important for SI, as is avoiding long wires that could cause crosscoupling problems. (In Synopsys' Physical Compiler® and Astro™ tools, you can limit wire length by using the max_net_length rule during optimization.) Even more important, do everything possible to reduce routing congestion, which helps reduce crosstalk. Easing congestion across the entire design and in specific local areas also makes SI problems easier to fix later because you have enough space to move victim and aggressor traces apart. Rules of thumb for deciding how much extra space is enough can be found in the Synopsys Professional Services white paper “Design Planning Strategies to Improve Physical Design Flows-Floorplanning and Power Planning” (http://www.synopsys.com/cgi-bin/sps/wp/dps/paper1.cgi). This paper also makes it clear that the rules have to suit the application, and the SI problems that occur in designs at 130-nm and smaller make the design-planning rules increasingly stringent. Floorplanning is vital for reducing long channels and congestion in general, always keeping the idea of maximizing resources in mind to prevent SI problems. Methods such as shielded feed-throughs help. More fundamental is the consideration of placement utilization as it relates to design size. More cells generally mean more congestion. Utilizing area recovery is therefore important, but apply this method carefully to paths that are close to zero slack because they could become SI victims. It is useful to take advantage of tool capabilities such as congestion-driven placement in Physical Compiler (physopt -timing_driven_congestion) tool. Astro tool's post-placement optimization (astPostPS1) is another option. This capability includes congestion-based coupling capacitance and noise estimation. When it comes to design planning for preventing SI problems, clock trees deserve extra attention. Their many levels of logic pose particular risks for crosstalk because each level may experience only a small amount of crosstalk-induced delay that accumulates to cause timing errors. Additionally, clock networks can be difficult to fix after routing. It is therefore worthwhile during floorplanning to triple-space clock network tracks, shield clock traces, constrain clocks to separate metal layers, and/or use higher-layer metal. Bear in mind that triple-spacing may not be sufficient, and shielding may lead to additional delay. Controlling transition time in synthesis is a good idea to scale-up drivers, as is the use of inverters and balanced buffers to minimize rise-versus-fall skew. Along with other types of design planning, power planning can play a big role in helping to avoid congestion and thus minimize noise. Power Network Analysis (PNA) in Jupiter™ tool can help reduce local congestion. If your design is especially large, consider using a shielded hierarchical design flow. A shielded flow helps avoid memory- and compute-capacity issues associated with analyzing and fixing SI problems. By not running top-level nets over or near blocks (within 10 microns), this flow prevents SI interactions between block and top-level nets. Using this approach reduces the need to run SI-related analyses for the entire flattened design because analyzing each block separately detects nearly all possible SI problems. If some nets must pass over a block in a shielded hierarchical design, it is better to design that block from the beginning with feedthroughs. These nets run through the block with buffers and appropriate constraints, and you treat them like any other signal nets when analyzing the block. Synthesis and constraining methods for avoiding SI issues At 130-nm and above, many nets may have SI-related timing delays, but most nets have no detectable SI problems. That picture changes at 90-nm. At this technology node, most paths show some amount of SI-related delay. Whether it is 3, 5 or 10 ps, these delays seem to pervade the entire design. The more gates in a path, the more time is lost, so that the many small delays can add up to big problems. Because the delays are so widespread, it is impossible to fix every one of them, so you must make margins big enough to account for the added delays. Setting healthy timing margins at the beginning of the flow and progressively relaxing them to your final goals works well. This progressive relaxation of timing margins is a good approach for minimizing SI problems and any other types of timing issues. The actual margins depend on the specific design and library in use, but for typical designs, somewhere around 20 to 25 percent of the clock period might be reasonable in Design Compiler® synthesis tool, 15 to 17 percent in Physical Compiler tool, 10 to 12 percent in Astro tool, and 7 to 10 percent at sign-off. For designs with clock speeds greater than about 500 MHz, these margins might begin at 10 to 15 percent for Design Compiler and range down to 3 to 5 percent at sign-off. Whatever the specific percentages used, the progressive reduction in margins reflects the flow's increasing accuracy as the design moves toward tape out. Realistic timing margins are especially important in SI work to account for the nature of the timing issues involved and known inaccuracies of extraction, Nonlinear Delay Models (NLDMs), simulation results versus SPICE, IR drop, and other factors that contribute to on-chip variation (OCV). In addition to fundamental inaccuracies, the statistical methods used in parasitic extraction may cause slightly different results from one run to another. After you change the design in one area, a timing error may appear in an untouched area. But if this timing error is within the extraction tool's statistical accuracy, the timing margins can cover for the problem, and you can ignore the error. In general, you need to sum the inaccuracies from all sources and set the overall design margin accordingly. Note that some libraries have 5 to 10 percent timing margin built-in, so additional margining during sign-off may be excessive. Unfortunately, information on library margins is often unavailable, whether the libraries are characterized internally or acquired from a third party. As with all SI tradeoffs, pessimism is the default position, yet the basic relationship between bigger margins and higher area penalties requires you to constrain the inclination toward excessive margins. In addition to general-purpose methods that prevent or minimize the impact of all timing issues, it is useful to take advantage of a methodology specifically targeted at reducing the likelihood of SI problems. This approach is based on the understanding that stronger drivers make nets less susceptible to aggressors. Setting aggressive transition times encourages the use of stronger drivers, and a good initial rule of thumb is 1 ns or less for max_transition time (30-70 percent trip points) in Design Compiler or Physical Compiler tools, although slower designs may suffice with larger levels. Basically, max_transition needs to parallel library characterization values, and most libraries have index points upwards of 1 ns. Setting a max_transition limit that is 25 to 50 percent of the maximum characterized transition time in the library is typically appropriate. Experiments with max_transition constraints have shown that as the values get smaller, area gradually increases until a point-a knee in the curve-at which area increases dramatically. The ideal setting for max_transition is just above this knee. In some 90-nm designs, that point is below 400 ps, so the range between 1 ns and 500 ps may be good. The tradeoffs with this technique are that stronger drivers take more area and power, and the driven nets are more likely to become crosstalk aggressors themselves. Also note that slow transition times can make SI analysis more pessimistic because arrival times are longer and therefore create bigger timing windows in which the net is susceptible to problems. As with general timing margins, you can set max_transition constraints aggressively at the placement/optimization stage and relax them a little at the post-route stage. SI Prevention in physical synthesis and routing As mentioned earlier, the best way to prevent crosstalk problems is to maximize area and routing resources. It can be helpful to keep this principle in mind when applying timing/area constraints in physical synthesis. For example, you can minimize the impact of aggressive max_transition time constraints by targeting them to timing-critical paths. Even with good prevention techniques, typical crosstalk-induced delays in the critical paths of 90-nm designs are around 15 percent of the clock period (as seen after routing). Applying more aggressive max_transition time constraints only to those paths can reduce the likelihood that they will become crosstalk victims, while avoiding the increase in area that would occur if you applied the more aggressive constraints to nets that are not in the critical range. This approach also helps limit the strength of potential aggressor nets. Another good technique for controlling area increases due to tight constraints is to apply area recovery during optimization. At the same time, avoid downsizing drivers of nets in the critical timing range (nets that have positive slack ranging from 0 to 15 percent of the clock period) because these nets may become crosstalk victims. In Physical Compiler tool, you can accomplish these goals by using the area_recovery option in the physopt command with the area_critical_range. In the Synopsys SI sub-flow, crosstalk prevention continues into the routing stage with efforts to avoid very dense routing areas. Based on estimations of coupling capacitance or actual noise calculations, the router should be able to estimate routing resources and allocate the net routing appropriately. The basic technique is to spread out the wires within the same Gcell and among different Gcells to reduce the routing density, usually in the global routing stage. During track assignment, you can make similar estimations to identify high-noise nets. Based on these estimations, the router attempts to avoid long parallel wires among the potential victim and aggressor nets. Even with all these precautions, SI problems will almost certainly appear after routing a design for technologies at or below 150-nm. For that stage of SI work, you need an analysis-and-repair sub-flow that eliminates critical problems in just a few iterations. You can find information about such a sub-flow in the Synopsys Professional Services white paper “Design Practices and Strategies for Efficient Signal Integrity Closure” (http://www.synopsys.com/cgi-bin/sps/wp/si/paper1.cgi). By reducing the number of crosstalk delays and timing errors, the SI problem prevention methods described here make the final analysis/repair sub-flow manageable and more predictable. The prevention methods thus shift some of the SI work to the front end of the design flow, where you can usually afford a little more time. That time is well spent, because it helps make all aspects of your design flow more predictable.
Figure 1-Methods for preventing signal integrity problems begin with design planning and continue into routing. Good prevention measures minimize the amount of find-and-fix work needed at the back end of the flow and help ensure predictable timing closure. Author's bio Todd Beck is a Senior Staff Consultant at Synopsys Professional Services specializing in SOC integration, chip-level STA, chip I/O timing, SI analysis and timing closure. He has worked on numerous ASIC design projects involving high-performance graphics, defense, networking, high-performance DSPs and HD television chipsets. He holds a BS degree in Computer Science from the University of Wisconsin and has two years of graduate study in EE at the University of Illinois. |
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