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Tech Papers Seamless PLM with Compliance Provides True Eco-design
Forward thinking Fortune 500 CEOs find that environmental sustainability strategies are …
Comprehensive Solution Space Simulation and Analysis, SiSoft (Signal Integrity Software, Inc.)
As system data rates approach and exceed 1 GHz, signal integrity and timing problems are causing
lengthy design iterations and field reliability problems. …
Automated Assembly and IP Integration Techniques for SoCs, Atrenta
Platform-based methodology is projected to become the dominant approach for SoC design in the very near future. Automated assembly techniques equally will become …
Presentations Jasper formal verification technology delivers compelling benefits throughout the entire SoC design flow, from RTL debug through verification and …
Jasper Design Delivers Targeted ROI, Jasper Design Automation
Jasper Design Automation deploys advanced formal verification technology for the competitive advantage of its customers, across the SoC design cycle …
CebaTech Corporate Presentation (PDF), CebaTech Inc.
CebaTech, Inc develops advanced ESL tools for semiconductor design, and uses these tools to create high‐value and complex IP in new and emerging markets …
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Jobs Lead Development Specialist / PCB - German Language for Mentor Graphics Corporation at Wilsonville, OR Technical Marketing Engineer - DFT for Mentor Graphics Corporation at Wilsonville, OR Software Development Engineer ( Functional Verification) for Mentor Graphics Corporation at San Jose, CA Principal Engineer - Place & Route for Mentor Graphics Corporation at San Jose, CA Lead Development Sepcialist / Functional Verification - French Language for Mentor Graphics Corporation at Wilsonville, OR Sr. Software Engineer - Place & Route (Routing, Timing & Optimization) for Mentor Graphics Corporation at San Jose, CA
Online Books Application-Specific Integrated Circuits (ASICs... the book), by Michael John Sebastian Smith.
Bit-Slice Design: Controllers and ALUs, by Donnamaie E. White.
Power, accuracy and noise aspects in CMOS mixed-signal design, by Sanduleanu, Mihai Adrian Tiberiu.
Verification Methodology Manual, 3rd Edition, by David Dempster and Michael Stuart.
Books For Sale
Forum Topics QUALCOMM Begins Utilizing 45 Nanometer Semiconductor Process
latest post : June 22, 2009, 11:48:pm Upcoming Events SEMICON West 2009 at Moscone Center San Francisco CA - Jul 14 - 16, 2009
Library Management with Altium Designer at Premier EDA Solutions Ltd. Stanstead Abbotts Ware Hertfordshire United Kingdom - Jul 14, 2009
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