Presented by EVE and Synopsys, this seminar promotes a new methodology
to address HW/SW Co-Verification of complex SOCs and ASICs.
This seminar already won great reviews and has been called "innovative", an "eye-opener" and "a must-see" by designers in the US and Japan.
Using lessons learned from real projects, the seminar provides a solution to the Billion Cycle Challenge. Whether your chip goes into a cell phone, a network router or a set-top-box, the Billion Cycle Methodology gives you a faster path to high-quality working silicon, including functional software, firmware, operating system & application.
Guest speakers from ST (Paris), ARM (Swindon) and TI (Munich) will present actual verification challenges & solutions based on their experience in designing complex SOCs.