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As clock frequencies and data rates soar, digital designers are being forced to account for the effects of degraded high-frequency signals, causing otherwise healthy bit streams to be unrecognizable at receiver ICs.
This technical forum will focus on simulation-based signal-integrity analysis of multi-gigabit interconnects. Methodologies for understanding and proactively dealing with multi-gigabit interconnect problems will be discussed, as well as future trends in IC technology.
Seminar attendees will gain a clear understanding of the following multi-gigabit design topics:

· Eye-diagram and jitter analysis using multi-bit stimuli
· Lossy-line and advanced via modeling
· Inter-symbol interference
· Integrated simulation with both HSPICE and IBIS
· Multi-gigabit system verification with Mentor Graphics ICX™ and HyperLynx GHz™
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