RTL Sign-off for Stratix® FPGA and SoC Designs
Join us for a webinar on
Feb 03, 2016 at 10:00 AM PST.
The Stratix® FPGA and SoC
family enables the delivery of
high-performance, state-of-the-art products to
market faster with lower risk and higher
productivity. By combining high density, high
performance and a rich feature set, Stratix
series FPGAs integrate more functions and
maximize system bandwidth.
Verification at the RTL stage of development
is essential to reduce valuable debug time
after implementation. The integration of
complex digital logic with third-party IP
makes the verification of clock-domain
crossing and reset-domain crossings a sign-off
requirement, since CDC errors are especially
difficult to debug.
The webinar will cover the requirements for
RTL sign-off including lint syntax and
semantic checks, clock-domain crossing
verification in the content of the FPGA flow.
A solution from Real Intent will be presented
that reflects the practical experience by FPGA
Rama Venkata from Intel and Ramesh Dewangan
from Real Intent will be the technical
After registering, you
will receive a confirmation email containing
information about joining the webinar.
View System Requirements