Attend Synopsys' Verification Seminars
February 24 - May 2004

As verification challenges continue to grow faster than chip complexity, new methodologies must be used to ensure first-pass silicon success. Come see an advanced verification methodology developed by industry expert Janick Bergeron, moderator of Verification Guild and a Synopsys principal R&D engineer, that addresses the immense challenge of verifying today's complex designs. Attendees will learn how to architect a scalable, reusable verification environment that takes advantage of the latest advances in constrained-random and design-for-verification solutions to maximize verification productivity. Janick Bergeron will be a featured speaker at various worldwide locations. Attend these FREE technical seminars and enter to win an Apple iPod.

 Topics covered include:
-Design-for-verification techniques
-Basic testbench methodology
-Advanced testbench methodology

Register now!
Various Worldwide Dates and Locations

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