Attend Synopsys' Verification Seminars
February 24 - May 2004
As verification challenges continue to grow faster than chip complexity,
new methodologies must be used to ensure first-pass silicon success. Come see an advanced
verification methodology developed by industry expert Janick Bergeron,
moderator of Verification Guild and a Synopsys principal R&D engineer,
that addresses the immense challenge of verifying today's complex designs.
Attendees will learn how to architect a scalable, reusable verification environment that takes advantage
of the latest advances in constrained-random and design-for-verification solutions to maximize verification productivity.
Janick Bergeron will be a featured speaker at various worldwide locations.
Attend these FREE technical seminars and enter to win an Apple iPod.
Topics covered include:
-Basic testbench methodology
-Advanced testbench methodology
Various Worldwide Dates and Locations
Trademarks/Copyright 2004 Synopsys, Inc. All Rights Reserved.
You are registered as: [_EMAIL_].
CafeNews is a service for EDA professionals. EDACafe respects your online time and Internet privacy. Edit or Change my newsletter's profile details. Unsubscribe from EDACafe.com sponsor newsletter.
Copyright © 2016, Internet Business Systems, Inc. — 595 Millich Dr., Suite 216 Campbell, CA 95008 — +1 (408)-337-6870 — All rights reserved.