NEW Verification Avenue Issue Now Available:
Check It Out!
Synopsys Verification Avenue - A technical bulletin for design and verification engineers with the latest product updates, in-depth technical articles, Q&As, and an extensive resource information section.
New Issue Highlights:
View the latest issue now!
- VCS (R) 7.2: New Features on Every Front
- System Studio Leads the Charge for ESL
- Successful Mixed-Language Code Coverage with VCS
The September issue was the most downloaded issue in Synopsys Verification Avenue history! If you missed this popular issue, you can still view it now!
Synopsys Verification at DVCon
2/14-16, 2005, San Jose, California
Register for the SystemVerilog Assertions tutorial presented by Ben Cohen and be eligible to receive a FREE copy of the new "SystemVerilog Assertions Handbook"! HURRY, seats are limited!
See What's New in Synopsys'
Discovery Verification Platform - Booth #306
Come see how the Synopsys VCS comprehensive RTL verification solution delivers up to 5X faster verification performance with its native, full-featured testbench, comprehensive coverage, and complete assertion technologies.
Hear how the DesignWare Verification Library provides the industry's broadest portfolio of design-proven, high-quality, standards-based verification IP to enable designers to save testbench development time and quickly reach their functional coverage goals.
SystemVerilog at DVCon
We Love SystemVerilog Cocktail Event - Entrance is FREE!
Come and share in the possibilities that SystemVerilog offers and get all your questions answered. The fun begins at 5 PM on February 14th in the DVCon Exhibit Hall. FREE passes to the Exhibit Hall are available upon registration.
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