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Attend Synopsys' SpringTech 2005 Seminars!

You're invited to the Synopsys SpringTech 2005 Seminars! This series includes both a Galaxy™ Design Seminar and a comprehensive DFM Seminar with the only U.S. DFM seminar coming up on Tuesday, May 10, 2005 at the Santa Clara Convention Center. We will also be holding a Galaxy Design Seminar at the same location on May 10.


Galaxy Design Seminars

Galaxy Seminar Overview

The challenges of chip design continue to grow; therefore the need for a systemic solution comprised of best-in-class tools is more critical to design success than ever before. This FREE seminar series features proven methodologies within the Galaxy Design platform for achieving the fastest path to silicon at 130nm and for successful transition to 90nm and beyond. Certain locations will include a demonstration of advanced multi-voltage techniques utilizing the ARM Intelligent Energy Manager (IEM) implemented in a reference design developed jointly by ARM and Synopsys.

Topics to be covered include:

  • RTL Synthesis
  • Physical Implementation
  • Signoff
  • Test Synthesis

    Dates, Locations and Agenda Details

    Who Should Attend?
    This seminar is recommended for designers and design managers who are designing at 90nm now or planning to use 90nm technology for their next design.

    Register Today!


    DFM Seminars

    DFM Seminar Overview

    These seminars will show you how our DFM product family addresses critical yield, manufacturability, and scalability issues for advanced designs to quickly improve yield and reduce turn around time. Get an overview of the importance of a comprehensive tool suite, as well as detailed sessions on each design stage, including: physical verification, mask synthesis, mask data prep, lithography verification and TCAD. By creating the critical links between each of the design, process and manufacturing steps you can achieve manufacturing made smarter.

    Topics to be covered include:

  • DFM Overview
  • TCAD For Manufacturing
  • Mask Data Prep (CATS)
  • Mask Synthesis & Lithography Verification
  • Physical Verification (Hercules)
  • TCAD

    Dates, Locations and Agenda Details

    Who Should Attend?
    This seminar is recommended for layout, process, lithography and manufacturing engineers and their managers who want to accelerate time-to-yield and ensure design manufacturability at 90 nm and smaller nodes.

    Register Now!


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