See Synopsys' Discovery Verification at DAC!
Verification Suite Demos
You're invited to see Synopsys Discovery verification solutions at DAC 2005 in Anaheim, CA!
Design Automation Conference (DAC) 2005
Anaheim Convention Center
Verification Suite Demos:
RTL Bug-Finding Technology with VCS® and Magellan
Discovery ESL Verification Solution with System Studio
Achieving Verification Closure with SystemVerilog featuring Synopsys Scientist Janick Bergeron
Every Synopsys verification suite demo at DAC will include a drawing to win one of the following books: SystemVerilog Assertions Handbook, A Practical Guide for SystemVerilog Assertions or a certificate for the upcoming SystemVerilog Verification Methodology Manual. Hurry seats are limited!
SystemVerilog User Forum Luncheon
Sponsored by Synopsys, Inc.
Marriott Anaheim Hotel, Marquis Northeast Ballroom
Monday, June 13, 2005
11:30am-1:30pm (Lunch is provided)
The use of SystemVerilog to increase design and verification productivity and quality is growing rapidly. This timely event provides a unique opportunity to hear from actual users about their SystemVerilog deployment experiences. Learn how your colleagues are benefiting from
Sign Up Today!
Assertion-based Verification with SystemVerilog Workshop
Sponsored by Doulos & Synopsys, Inc.
Anaheim Convention Center, Room 202A
Thursday, June 16, 2005
11:30am-2:00pm (Lunch is provided)
Presented by Doulos and Synopsys, this workshop provides an introduction to assertion-based verification using SystemVerilog. You will learn how SystemVerilog assertions are used in today's design process and see a demonstration of their use with Synopsys' VCS comprehensive RTL verification solution and Magellan hybrid formal analysis tool.
Accellera's SystemVerilog Booth at DAC
Visit Booth #2284
Accellera has taken Verilog to the next level of productivity and usefulness through development of SystemVerilog, a set of extensions to the Verilog language, to aid in the creation and verification of abstract architectural level models. The SystemVerilog community of suppliers will demonstrate products and services to showcase this widely-supported language standard. There are three major sponsors anchoring the booth including Mentor Graphics, Synopsys and Cadence, and many other companies will give scheduled demonstrations during exhibit hours including a "Meet the Experts" discussion area. Come see a live demonstration of Synopsys' proven SystemVerilog solutions for synthesis, formal and verification.
ESL Now! at DAC
More than twenty companies are joining together to spread awareness of electronic system-level (ESL) design and verification tools and methodologies, through a campaign culminating at the upcoming Design Automation Conference (DAC) in Anaheim, California. We are inviting users to participate in a short, online survey regarding their current and planned ESL tool usage. The survey results will be compiled and announced after DAC. Respondents will be entered to win one of several Sony PSP (PlayStation Portable) video game systems.
Visit our ESL website and help influence the future!
We look forward to seeing you in Anaheim at DAC!
The Synopsys Verification Team
Trademarks/Copyright 2005 Synopsys, Inc. All Rights Reserved.