Converge to Silicon Success with Synopsys at DAC 2005!
Synopsys continues to bring the industry's most exciting and innovative products to market including: IC Compiler, our next-generation physical design system; PrimeRail, for power network signoff; and VCS® for comprehensive verification in Booth #1088. To see our complete analog-mixed signal solution now complemented with HSIM® and HSIMplus, visit us in Booth #700. For more details, please visit our DAC website.
See how Synopsys' best-in-class design and verification platforms, DFM solutions, comprehensive IP portfolio, analog mixed-signal solutions, and design services enable development of the most complex systems-on-chips (SoCs).
Register Today to Attend our Suite Demos!
Analog Mixed-Signal Solutions
Analog and Digital Library Design with Circuit Explorer
Discovery AMS Overview: Production Proven Mixed-Signal Verification
HSIM & HSIMplus 6.0 release update
Hierarchical Post-Layout Verification
Nassda Acquisition Update
Tackle DFY/DFM Challenges in Standard Cell Libraries with Cadabra
Design for Manufacturing
Hercules: Full-chip Verification in Hours; Full-chip Short-finding in Minutes
Synopsys DFM Solutions: Faster TAT and Higher Yield
Methodology Considerations to Optimize for Power in 90-nm SoCs
Design Compiler® RTL Synthesis Roadmap
IC Compiler: Physical Implementation
PrimeRail: Extending Signoff to Power Networks
A Proven Path to Add PCI Express® to Your Designs
AMBA 2.0 Technology-based Subsystem Design in a Jiffy -- Easing the Transition to AMBA 3 AXI
Reduce Interface and Schedule Risks: Design with Certified USB IP
Altera® Structured ASICs for ASIC Designers
AMD Opteron - Performance and TCO Leadership in EDA Environments
Comprehensive Verification of AMBA 3 AXI Based-systems
Design for Low Power with Synopsys Galaxy and ARM1176 IEM-enabled Cores
Fast SPIRIT IP-based SoC Design from ESL through GDSII
Synopsys Galaxy and Discovery Platform Support for IBM-Chartered 90-nm Process
TSMC Reference Flow - Integrating Design and Process
Xilinx® Advanced FPGA Design Flow for Prototype and Production Applications
UMC-Synopsys Reference Design Flow for UMC's Advanced Deep Submicron Processes
Achieve Verification Closure with SystemVerilog - Featuring Synopsys Scientist Janick Bergeron
Discovery ESL Verification Solution with System Studio
RTL Bug-Finding Technology with VCS and Magellan
Visit our Synopsys Partner Booth #1379
This booth is dedicated to the "Partnering For Silicon Success" initiative. Exhibits at this booth will showcase partner collaborations with industry leaders ARM and TSMC. These collaborations bring the most advanced silicon processes, high-quality IP and best-in-class IC design solutions to the global electronics market and enable the convergence of developing and producing complex SoCs.
Be sure to attend these Events:
SystemVerilog User Forum Luncheon
June 13: 11:30am to 1:30pm, Marriott Hotel, Marquis Northeast Ballroom
Synopsys-IBM Power Luncheon
June 14: 11:30am to 1:00pm, Rooms: 303AB
Synopsys Breakfast: Enabling Complex Designs with Advanced Libraries and IP
June 15: 7:30am to 10:00am, Marriott Hotel, Marquis North Ballroom
ARM-Synopsys Luncheon: What's Cool/Hot with Low-power Solutions
June 15: 11:30am to 2:00pm, Room: 204B
Assertion-based Verification with SystemVerilog Workshop
June 16: 11:30am to 2:00pm, Room: 202A
We look forward to seeing you at DAC!
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