NEW Verification Avenue Issue Now Available

SystemVerilog Tutorial and News
  • October 6, Technical Tutorial: "Verification Methodology Manual (VMM) for SystemVerilog"
  • Synopsys Introduces Pioneer-NTB for SystemVerilog Testbench Automation
  • Springer Publishes "ARM-Synopsys Verification Methodology Manual for SystemVerilog"
  • eScape to SystemVerilog Seminar Available Online


Technical Tutorial
Using the "Verification Methodology Manual (VMM) for SystemVerilog"
Thursday, October 6
9:15 - 11:00 AM
Santa Clara Convention Center, USA
ARM Developers' Conference

This tutorial, developed by Doulos in partnership with Synopsys and ARM, delivers a practical explanation of the key technical and organizational features of the "VMM for SystemVerilog," authored by Janick Bergeron and Eduard Cerny from Synopsys and Alan Hunter and Andrew Nightingale from ARM. It highlights the benefits of the methodology and illustrates how users can construct VMM-compliant verification environments powered by ready-to-use class libraries specified in the book. The discussion emphasizes measurement of verification completeness and productivity through proper use of SystemVerilog's functional coverage features. This provides a quantitative basis for the verification effort and attendees will gain insight in how to establish verification as a mature engineering discipline within their organizations.

Special Book Signing Event
After the tutorial at 11 AM, we hope you'll join Synopsys and ARM for a special book-signing event with the authors of the VMM.

There are a limited number of free tutorial passes available,
so register now:

http://www.doulos.com/content/events/VMMTut.php




Synopsys Introduces Pioneer-NTB for SystemVerilog Testbench Automation

Synopsys today announced Pioneer-NTB, a new SystemVerilog testbench automation tool. Built on proven VCS ® and Vera® technologies, Pioneer-NTB enables engineers to deploy a standards-based advanced verification environment for their VHDL, Verilog and mixed-HDL designs running on third-party simulators. Pioneer-NTB users have immediate access to the extensive Vera and VCS ecosystems, including Reference Verification Methodology, verification IP, assertion IP, debug/analysis and worldwide expert support.

Pioneer-NTB also supports OpenVera® testbenches. Existing Vera environments can be easily migrated to Pioneer-NTB for up to 2x faster verification runtime performance utilizing Pioneer-NTB's compiled testbench technology. Vera to Pioneer-NTB migration documentation is available with the tool.

Pioneer-NTB and Vera will be packaged together as a single product, allowing Vera customers to take advantage of Pioneer-NTB with no additional charge. Synopsys will continue to develop, enhance and support Vera, enabling existing customers to adopt Pioneer-NTB at their own schedule.

More information is available at:
http://www.synopsys.com/products/simulation/pioneer/pioneer_ntb.html




ARM-Synopsys "Verification Methodology Manual (VMM) for SystemVerilog" Is Here!

Springer Science+Business Media, Inc, a major publisher of professional books and research journals in engineering, announced the availability of the ARM-Synopsys book "Verification Methodology Manual for SystemVerilog." This is the result of collaboration between ARM and Synopsys, and peer review by over 30 semiconductor companies and industry experts. The "VMM for SystemVerilog" provides a blueprint for system-on-chip verification success using SystemVerilog and is destined to become an instant classic reference for the industry.

For more information visit:
http://www.vmm-sv.org/




eScape to SystemVerilog Seminar Available Online
The eScape to SystemVerilog seminar, now available online via Demos on Demand, provides guidance on transitioning to SystemVerilog for verification by showing and contrasting language capabilities and how common verification structures and techniques can be implemented using SystemVerilog. Learn practical and up-to-date guidance on transitioning to a standards-based verification methodology built on SystemVerilog. This seminar will be particularly valuable to those using the 'e' language, although there's ample technical content for users of other verification and hardware description languages, including OpenVera., Verilog and VHDL.

For more information visit:
http://www.demosondemand.com/dod/feat_cont/seminars/systverilog.aspx


Trademarks/Copyright 2005 Synopsys, Inc. All Rights Reserved.
UNSUBSCRIBE: If you no longer wish to receive Verification updates from Synopsys, please send an email to unsubscribe_vg@synopsys.com. To be removed from all Synopsys updates, send an email to unsubscribe@synopsys.com.

You are registered as: [_EMAIL_].

CafeNews is a service for EDA professionals. EDACafe respects your online time and Internet privacy. Edit or Change my newsletter's profile details. Unsubscribe from EDACafe.com sponsor newsletter.

Copyright © 2016, Internet Business Systems, Inc. — 595 Millich Dr., Suite 216 Campbell, CA 95008 — +1 (408)-337-6870 — All rights reserved.