Be sure to take advantage of Synopsys Verification Seminars, the new issue of Verification Avenue and hot news and events.
- Practical Verification with SystemVerilog Seminars, locations worldwide, March - July
- New Issue of Verification Avenue
- First Complete SystemVerilog Design and Verification Flow
- Verification Tutorial at Embedded Systems Conference
Practical Verification with SystemVerilog Seminars
Free Seminars start March and run through July
Learn practical techniques for using Discovery™ Verification solutions to address design complexity.
Stay to the end to be eligible to win an iPod Nano or a
Verification Methodology Manual (VMM) for SystemVerilog book.
- SystemVerilog Solution Update
- Architecting a Practical Verification Environment
- Tips for Building a Verification Environment
- Best Practices of Functional Coverage
- Practical Debugging of Designs and Assertions
- Mixed-Signal Verification Techniques
For dates, worldwide locations, and registration, please visit:
New Issue of Verification Avenue!
The Synopsys Verification Avenue - A technical bulletin for design and verification engineers with the latest product updates, in-depth technical articles and Q&As.
March 2006 Issue
Issue highlights include:
View the latest issue!
- Product Updates: Vera®, Leda®, Magellan™, System Studio, DesignWare® Verification IP and Formality®
- Pioneer-NTB Enables SystemVerilog Testbench Automation
- DesignWare Verification IP Support of the Verification Methodology
Manual (VMM) for SystemVerilog
- Transaction-Level Modeling: SystemC and/or SystemVerilog
First Complete SystemVerilog Design and Verification Flow!
Verification IP Library for SystemVerilog!
Synopsys recently announced the industry's first complete SystemVerilog design and verification flow. As part of this flow, Synopsys introduced a new native SystemVerilog parser in Formality. In addition, Synopsys announced that the VCS® Verification Library is the first to support SystemVerilog and the Verification Methodology Manual (VMM) for SystemVerilog.
To learn more about Synopsys' SystemVerilog solutions visit:
Embedded Systems Conference Silicon Valley
April 3-7, 2006
San Jose, CA
Synopsys Technical Tutorial
SystemC™ and SystemVerilog for Electronic System-Level Design
Visit the ESC website to register for this valuable event.
Trademarks/Copyright 2006 Synopsys, Inc. All Rights Reserved.