New Issue of Verification Avenue!
The Synopsys Verification Avenue - A technical bulletin for design and verification engineers with the latest product updates, in-depth technical articles and Q&As.
October 2006 Issue
- SystemVerilog-OpenVera® Interoperability in VCS®
- Moving to the Next Level in Verification Productivity and Predictability
- Accelerating Functional Closure
- Understanding the Key Elements of a VMM-based Testbench
View the latest issue!
The Art of Verification with SystemVerilog Assertions (SVA) NEW!
by Faisal I. Haque, Jonathan Michelson, Khizer A. Khan
The Art of Verification with SystemVerilog Assertions teaches the SVA language and its usage with both simulation and formal verification (model checking). SVA syntax and features are explained in simple and very easy-to-understand language. The usage of Booleans, sequences, properties, and assertion layer directives are illustrated with both simple examples and examples drawn from common verification problems.
After SVA syntax and semantics are covered, assertion-based verification techniques are explained, as are model-checking techniques. Covered subjects include where to add checking and coverage assertions, who writes assertions, assertion libraries, and assertion-coding guidelines. These techniques are used to develop an effective, SVA -based verification strategy for a real-world design.
Learn More: http://www.verificationcentral.com/sva_book.html
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