EE Times Virtual Conference: System-on-Chip, Designing Next Gernation SoCs taking place on Wednesday, September 16, 2009 at 11am - 6pm EDT.

Join us on Wednesday, September 16th
for the EE Times System-on-Chip
Virtual Conference

This virtual conference explores the challenges faced by developers of ASIC- and FPGA-based SoCs, including an in-depth look at the state of chip design economics, the quest for plug-and-play intellectual property, the state of the verification bottleneck, and the need for better integration between analog and digital design flows. Register today for System-on-Chip Virtual Conference: Designing Next Generation SoCs, Wednesday, September 16th, 11am-6pm EDT.

Register Today for the EE Times Power Management Conference

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Join EE Times for a one day Virtual Conference: Systems-on-Chip, Designing Next Generation SoCs, Wednesday, September 16th.

This conference will be of interest to hardware and embedded software management, including systems architects, system designers, embedded system designers, and ASIC- and FPGA-based SoC developers.

Don't miss this complimentary virtual conference.

Attend and hear from our two keynotes on SoC: The Next Generation.

Rajeev Madhavan, CEO, Magma

Deriving ROI from Next-Generation SoCs
Rajeev Madhavan, CEO, Magma

In this presentation, Rajeev Madhavan of Magma Design Automation will outline what it takes to make SoC design profitable. He'll describe the changes that are needed in both design tools and licensing models. He'll explain how to improve the productivity of analog and mixed-signal designers, how to leverage higher levels of automation and faster verification to speed turnaround time, and more importantly, what it takes to enable analog design reuse. He'll also discuss how changes to software licensing models will benefit both designers and software providers.


Gerry Gaffney, President, Altium, USA


Design Innovation Beyond SoC

Gerry Gaffney, President, Altium, USA

In this presentation, Gerry Gaffney, President of Altium, USA, will discuss the design approach and tool systems needed to allow all parts of the design process to work together in a flexible and constructive way, and in the process exploit the full potential of FPGA-based SoCs. The approach transcends the constraints of traditional ASIC-based SoC or hardware-centric design by harnessing FPGAs as a highly flexible system platform that, along with hosting soft devices in the familiar sense, can form a soft-hardware interface layer and connectivity backbone for the entire design. This opens up a new approach to system-level electronics design that provides the design freedom and flexibility needed to create tomorrow's innovate products.

Conference Co-Chairs: Clive (Max) Maxfield, Vice President, TechBites International, Dylan McGrath, Online Editor, EE Times and Nic Mokhoff, Research Editor, EE Times.


Join
us on Wednesday, September 16th, as we explore the challenges faced by developers of ASIC- and FPGA-based SoCs, including an in-depth look at the state of chip design economics, the quest for plug-and-play intellectual property, the state of the verification bottleneck, and the need for better integration between analog and digital design flows.

We will be covering four distinct content areas:

  • Verification: Verification is the single biggest challenge in the design of SoC devices and reusable IP blocks. In this session, we will be covering Architecture-related verification, RTL debug, Formal Verification, and Verification in light of IP design re-use.
    • Moderator: Clive (Max) Maxfield, Vice President, TechBites Interactive
    • Panelist: Brian Bailey, independent consultant
    • Panelist: Additional anelists to be announced shortly
  • Intellectual Property: This panel will explore the quality of IP cores, the lack of standards/quality metrics and the business dynamics of the IP business. We will also talk about the near- and long-term futures of the IP business, and propose solutions that will work for IP suppliers and their customers.
    • Moderator: Dylan McGrath, West Coast Online Editor, EE Times
    • Panelist: Tom Feist, Sr. Marketing Director, ISE Design Suite, Xilinx, Inc.
    • Panelist: John Goodenough, Director, Design Technology, ARM Inc.
    • Panelist: James Aldis, Senior Member of Group Technical Staff, Texas Instruments
  • Analog/Digital Integration: In this session, we will discuss the various analog/digital simulators and how effective they communicate with each other, how designers can take full advantage of available tools for the intricately specific applications they are designing, how do ASIC- and FPGA-based SoC design flows differ for different application areas and other design flow integration issues will be discussed by tool developers, chip designers, and FPGA vendors.
    • Moderator: Clive (Max) Maxfield, Vice President, TechBites Interactive
    • Panelists: To be announced shortly
  • The Economics of Chip Design: This panel will examine the state of the economics of different forms of SoC design, delve into specific areas of increasing costs (verification, etc.) and try to ascertain whether there is any relief on the horizon.
    • Moderator: Dylan McGrath, West Coast Online Editor, EE Times
    • Panelist: Hitesh Patel, Director, ISE Foundation Product Marketing, Xilinx, Inc.
    • Panelist: Grant Martin, Chief Scientist, Tensilica, Inc.
    • Panelist: Ron Collett, Co-founder, president and CEO, Numetrics
  • What's Your Biggest Design Disaster? There's nothing quite like the experience of proudly powering up a new design for the first time ... and watching the sparks fly as everyone dives for cover. I could tell you some tales... I bet you could do the same (grin). Why not join Clive (Max) Maxfield, Vice President, TechBites Interactive in this interactive chat session and we'll swap 'war stories from the trenches'.

The System-on-Chip Virtual Conference provides the same opportunities as a face-to-face event:
Register Today for the EE Times Power Management Conference
  • Submit questions during live Q&A sessions with industry experts
  • Chat with fellow attendees on our floor and communications lounge
  • Collect and gather information from experts and vendors
  • Exchange virtual business cards
  • Opportunities to win great prizes

Platinum Prize: Kindle 6" Wireless Reader. Approximate Value of $350. Gold Prize: iPod Nano, 8GB. Approximate Value of $149. Silver Prize: $100 AMEX Gift Card. Approximate Value of $100.

Platinum Sponsor: Xilinx, Gold Sponsors: Actel/Avnet, ARM and Synopsys. Silver Sponsor: ISilicon Systems


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