You are receiving this email as a EDA Cafe subscriber on behalf of EE Times =============================================================================== EE Times System-on-Chip Virtual Conference Date: Tuesday, August 18, 2009 Time: 11:00am - 6:00pm EDT Where: From the Comfort of Your Desk Register Today at: Time is running out to register for the EE Times System-on-Chip Virtual Conference With just a day to go, we just wanted to make sure you've had the opportunity to register for tomorrow's EE Times System-on-Chip (SoC) Virtual Conference. We have a packed agenda as well as great prizes that we and our sponsors will be giving away. Why You Should Attend This Virtual Conference: > Easy to use platform > Excellent content > The convenience of not having to travel > The ability to handle your daily work load while attending Who Should Attend This Virtual Conference: > Hardware Management > Embedded Software Management > Systems Architects > System Designers > Embedded System Designers > ASIC-based SoC Developers > FPGA-based SoC Developers Don't miss this complimentary virtual conference. In addition to our keynotes: Gerry Gaffney, President, Altium, USA and Rajeev Madhavan, CEO, Magma, here are some additional reasons on why you should be attending next week's EE Times System-on-Chip Virtual Conference. Verification: Verification is the single biggest challenge in the design of SoC devices and reusable IP blocks. In this session, we will be covering Architecture-related verification, RTL debug, Formal Verification, and Verification in light of IP design re-use. - Moderator: Clive (Max) Maxfield, Vice President, TechBites Interactive - Panelist: Brian Bailey, independent consultant - Panelist: Janick Bergeron, Fellow, Synopsys - Panelist: Nick Heaton, Senior Architect, Cadence - Panelist: Tom Sandoval, CEO, Calypto Design Implementing Designs at Leading Edge Process Nodes: Meet with Andrea Cosmim, ARM Physical IP Division, to discuss your challenges in implementing designs at advanced process nodes. Andrea will highlight how ARM is partnering with industry leaders (such as foundries and EDA vendors) to enable a complete physical IP libraries and SoC implementation solution. Intellectual Property: This panel will explore the quality of IP cores, the lack of standards/quality metrics and the business dynamics of the IP business. We will also talk about the near- and long-term futures of the IP business, and propose solutions that will work for IP suppliers and their customers. - Moderator: Dylan McGrath, West Coast Online Editor, EE Times - Panelist: James Aldis, Senior Member of Group Technical Staff, Texas Instruments - Panelist: Tom Feist, Sr. Marketing Director, ISE Design Suite, Xilinx, Inc. - Panelist: John Goodenough, Worldwide Director of Design Technology, ARM Inc. - Panelist: Ian Mackintosh, Chairman and President, OCP-IP Mixed-Signal Embedded System Design Challenges:Analog becoming too demanding? Is programmable logic encroaching your SoC world? Is RTL knowledge a requirement? What design tools do you like? What capabilities would you like to see in SoC tools? What Mixed-Signal SoC design challenges keep you up at night? Should you design ground-up ASIC, or consider Mixed-Signal FPGAs as an alternative? Come join us for this sponsored chat and share your thoughts and see what your peers are saying. - Moderator: Venkatesh Narayan, Director of Software & Systems Engineering, Actel EDA in 2020: Join Dylan McGrath in this sponsored chat as we discuss what will the EDA industry look like in 2020. Will the economic and technical forces at work leave it looking the same? Or dramatically different? How so? Will the same three vendors still dominate? Will startup activity continue to serve as the industry's innovation engine? Come put in your two cents and see what others are saying. Addressing the Performance Bottleneck in Modern SOC Design - Serial IO Connectivity: This sponsored session presented by Panch Chandrasekaran, Sr. Product Marketing Manager, High-Speed Serial I/O, Xilinx, covers Xilinx's comprehensive serial IO portfolio which addresses challenging SoC requirements across the serial performance spectrum, from mainstream through ultra high-end applications. Hear Xilinx reveal how they are extending the high-performance end of the serial connectivity portfolio. Analog/Digital Integration: In this session, we will discuss the various analog/digital simulators and how effective they communicate with each other, how designers can take full advantage of available tools for the intricately specific applications they are designing, how do ASIC- and FPGA-based SoC design flows differ for different application areas and other design flow integration issues will be discussed by tool developers, chip designers, and FPGA vendors. - Moderator: Clive (Max) Maxfield, Vice President, TechBites Interactive - Panelist: Jim Davis, Vice President, Software and Systems Engineering, Actel - Panelist: Robert Hum, Vice President and General Manager, Deep Submicron Division, Mentor - Panelist: Ashutosh Mauskar, Vice President, Custom Design Business Unit, Magma - Panelist: Ralph Morgan, Vice President of Engineering, Synopsys System Prototyping - Virtual, FPGA or Hybrid? In this sponsored schedule chat, we will review ways to accelerate project cycles, hardware teams try to start hardware/software validation, hardware verification and interface tests to real-world stimulus as soon as possible. Virtual platforms and FPGA-based rapid prototypes are just two of the alternative engines to execute your design prior to RTL and silicon availability. Does the emergence of virtual prototyping mean the end for FPGA-based prototypes? Will the hardware prototype continue to live on as an integral part of the SOC design cycle? Will hybrids of virtual and hardware prototypes be the answer? Join this chat session to discuss with our experts on the future of system prototyping. - Moderator: Frank Schirrmeister, Director, Product Marketing, System-Level Solutions, Synopsys, Inc. - Panelist: Tom Borgstrom, Director, Solutions Marketing, Synopsys, Inc. - Panelist: Juergen Jaeger, Director, Product Marketing, Synopsys, Inc. What's Your Biggest Design Disaster? There's nothing quite like the experience of proudly powering up a new design for the first time ... and watching the sparks fly as everyone dives for cover. I could tell you some tales... I bet you could do the same (grin). Why not join Clive (Max) Maxfield, Vice President, TechBites Interactiveme in this interactive scheduled chat session and we'll swap "war stories from the trenches". Economics of Next-Generation SoC Design: This panel will examine the state of the economics of different forms of SoC design, delve into specific areas of increasing costs (verification, etc.) and try to ascertain whether there is any relief on the horizon. - Moderator: Dylan McGrath, West Coast Online Editor, EE Times - Panelist: Sven Andersson, ASIC FPGA Designer, Realtime Embedded AB - Panelist: Ron Collett, Co-founder, President and CEO, Numetrics - Panelist: Steve Douglass, Vice President, Product Development, Xilinx, Inc. - Panelist: Grant Martin, Chief Scientist, Tensilica, Inc. The System-on-Chip Virtual Conference provides the same opportunities as a face-to-face event: * Submit questions during live Q&A sessions with industry experts * Chat with fellow attendees on our floor and communications lounge * Collect and Gather information from experts and vendors * Exchange virtual business cards * Opportunities to win great prizes Platinum Prize: One (1) Kindle 6" Wireless Reader. Approximate value of $350. Gold Prize: One (1) iPod Nano, 8 GB. Approximate value of $149. Silver Prize: One (1) $100 AMEX Gift Card. Approximate value of $100. View the give-away rules at: In addition, be sure to visit the exhibit hall for more opportunities to win prizes from our sponsors: Achronix Semiconductor: One (1) iPod Touch, 8GB. Approximate value of $229. ARM: One (1) $100 Amazon Gift Card. Approximate value of $100. Cadence: See what prizes you are eligble to win at: Isilon Systems: One (1) Kodak Zi6 HD Pocket Video Camera. Approximate value of $179. Synopsys: Five (5) $100 Amazon Gift Cards. Approximate value of $100 per gift card. Xilinx: Two (2) SP601 Eval Kits from Xilinx. Approximate value of $295 per kit. Ten (10) Apple iPod Shuffles, 2nd Gen 2GB. Approximate value of $50 per iPod. Platinum Sponsor: Xilinx Gold Sponsors: Actel/Avnet, ARM and Synopsys Silver Sponsor: Archronix Semiconductor Corporation, Cadence and iSilicon Systems Presented by: EE Times ------------------------------------------------------------------------- To opt-out of receiving promotions for the EE Times System-on-Chip Virtual Conference, please click here: TechInsights, a division of United Business Media LLC, respects your privacy. By registering for this event we may contact you regarding your event registration and other relevant TechInsights products and services such as webinars, research publications and events. Additionally, if you sign up for a sponsored session your contact information will be shared with the sponsor. Please read our Privacy Policy for further details at: TechInsights, a division of United Business Media LLC 600 Community Drive, Manhasset, NY 11030 - USA =============================================================================== You are subscribed as [_EMAIL_]. If you no longer want to receive news from our EDA sponsors but want to continue receiving other EDA newsletters, please visit Otherwise, if your email client supports HTML, please change your format preference to "HTML" for the best viewing experience. To change your personalized CafeNews mailing subscription, go to Copyright (c) 2016. Internet Business Systems, Inc. All rights reserved