Why not Use the Industry's Most Flexible PLL in your next ASIC Design?
MOSAID Virtual Silicon has the industry's first delta-sigma, fractional-N digital frequency synthesizer PLL for general purpose CMOS.
Here are some top reasons to use the innovative MOSAID fractional PLL in your next design:
- Optimize power management - Due to fine frequency control an ASIC with a true fractional
PLL typically uses 15% less active power than with a simple integer PLL. Additionally, the fractional PLL uses only 1.1mW
at 400MHz and it further reduces power loss by locking faster than typical PLLs.
- Reduce PLL area - with an area size of only 0.044mm2, the fractional PLL is placeable in
either the I/O ring or in the core, increasing flexibility in chip design.
- Design with flexibility - Perform true 26-bit fractional multiplication, generating any
frequency from 34.7 kHz to 3000 MHz, using any input from 1MHz to 300MHz. With a low cycle-to-cycle jitter
of +/- 15 ps peak to peak max at 400 MHz for DDR2 operation, the fractional PLL outperforms the alternatives giving the designer more timing flexibility. It's real and it's silicon proven in several processes.
- Generate any frequency from one low cost crystal - By allowing elimination of the external
clock IC, the VCXO or multiple crystals, the true fractional PLL can provide a reduction in ASIC and PCB bill
of materials cost and a corresponding reduction in overall system cost by up to $4.00.
Still not convinced?
Login or Register in our Customer Center to review the complete paper detailing why you should choose the MOSAID
Virtual Silicon PLL for your next design or to download the datasheet.
Please contact MOSAID Virtual Silicon with additional questions at
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