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Part Number :	D16750
Overview :
The D16750 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C750. The D16750 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 64 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. D16750 performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU.
Features :	- Software compatible with 16450, 16550 and 16750 UARTs - Configuration capability - Separate configurable BAUD clock line - Two modes of operation: UART mode and FIFO mode - Majority Voting Logic - In the FIFO mode transmitter and receiver are each buffered with 16 byte or 64 byte FIFO to reduce the number of interrupts presented to the CPU - Optional FIFO size extension to 128, 256 or 512 Bytes - Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data - In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data - Independently controlled transmit, receive, line status, and data set interrupts - False start bit detection - 16 bit programmable baud generator - MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD) - Programmable automatic Hardware Flow Control logic through Auto-RTS and Auto-CTS - Fully programmable serial-interface characteristics: - 5-, 6-, 7-, or 8-bit characters - Even, odd, or no-parity bit generation and detection - Baud generation - Complete status reporting capabilities - Line break generation and detection. Internal diagnostic capabilities: - Loop-back controls for communications link fault isolation - Break, parity, overrun, framing error simulation
Categories :	Controller
Portability :	ASIC FPGA FPGA Technologis Altera : APEX 20KC APEX 20KE APEX II Arria GX Arria II GX Cyclone Cyclone II Cyclone III FLEX 10K HardCopy HardCopy II HardCopy Stratix MAX II Stratix Stratix GX Stratix II Stratix II GX Stratix III Stratix IV Lattice : ispClock ispMACH 4000 LatticeEC/ECP LatticeECP2 LatticeECP2M LatticeECP3 LatticeSC LatticeSCM LatticeXP LatticeXP2 MachXO MachXO2 Platform Manager Power Manager II Xilinx : Artix-7 Kintex-7 Kintex-7 -2L Spartan-3 Spartan-3 XA Spartan-3A Spartan-3A DSP Spartan-3A DSP XA Spartan-3A XA Spartan-3AN Spartan-3E Spartan-3E XA Spartan-6 Spartan-6 -1L Spartan-6 HXT Spartan-6 LX Spartan-6 LXT Spartan-6 XA Spartan-6 XC Virtex-4 Virtex-4 FX Virtex-4 LX Virtex-4 SX Virtex-4 XA Virtex-5 Virtex-5 FX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SX Virtex-5 SXT Virtex-5 TXT Virtex-6 Virtex-6 -1L Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Virtex-7 Virtex-7 -2L Virtex-7 XT Virtex-7 XT Virtex-7T Virtex-II Pro Zynq-7000
Type :	Soft
Deliverables :	- Source code: VHDL Source Code or/and VERILOG Source Code or/and FPGA Netlist - VHDL & VERILOG test bench environment: Active HDL automatic simulation macros, ModelSim automatic simulation macros, NCSim automatic simulation macros, Tests with reference responses - Technical documentation: Installation notes, HDL core specification, Datasheet - Synthesis scripts - Example application - Technical support: IP Core implementation support, 3 months maintenance, Delivery the IP Core updates, minor and major versions changes, Delivery the documentation updates, Phone & email support