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Part Number :	DSPI_FIFO-APB
Overview :
The DSPI_FIFO-APB is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. The DSPI_FIFO-APB uses APB bus on the parallel interface side. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. The DSPI_FIFO-APB data are simultaneously transmitted and received. The DSPI_FIFO-APB is a technology independent design that can be implemented in a variety of process technologies.
Features :	- Compliant with AMBA specification, Revision 2.0 - SPI Master - Master and Multi-master operations - Two modes of operation: SPI mode and FIFO mode - 8 SPI slave select lines - System error detection - Mode fault error - Write collision error - Interrupt generation - Supports speeds up ¼ of system clock - Bit rates generated 1/4 - 1/512 of system clock. - Four transfer formats supported - SPI Slave - Slave operation - Two modes of operation: SPI mode and FIFO mode - System error detection - Interrupt generation - Supports speeds up ¼ of system clock - Four transfer formats supported - Fully synthesizable - Two DMA Modes allows single and multi-transfer - In the FIFO mode transmitter and receiver are each buffered with 16/64 byte FIFO's to reduce the number of interrupts pre-sented to the CPU - Optional FIFO size extension to 128, 256 or 512 Bytes - Static synchronous design - Positive edge clocking and no internal tri-states - Scan test ready
Categories :	Communication/Networking Microprocessor
Portability :	ASIC FPGA FPGA Technologis Altera : APEX 20KC APEX 20KE APEX II Arria GX Arria II GX Cyclone Cyclone II Cyclone III FLEX 10K HardCopy HardCopy II HardCopy Stratix MAX II Stratix Stratix GX Stratix II Stratix II GX Stratix III Stratix IV Lattice : ispClock ispMACH 4000 LatticeEC/ECP LatticeECP2 LatticeECP2M LatticeECP3 LatticeSC LatticeSCM LatticeXP LatticeXP2 MachXO MachXO2 Platform Manager Power Manager II Xilinx : Artix-7 Kintex-7 Kintex-7 -2L Spartan-3 Spartan-3 XA Spartan-3A Spartan-3A DSP Spartan-3A DSP XA Spartan-3A XA Spartan-3AN Spartan-3E Spartan-3E XA Spartan-6 Spartan-6 -1L Spartan-6 HXT Spartan-6 LX Spartan-6 LXT Spartan-6 XA Spartan-6 XC Virtex-4 Virtex-4 FX Virtex-4 LX Virtex-4 SX Virtex-4 XA Virtex-5 Virtex-5 FX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SX Virtex-5 SXT Virtex-5 TXT Virtex-6 Virtex-6 -1L Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Virtex-7 Virtex-7 -2L Virtex-7 XT Virtex-7 XT Virtex-7T Virtex-II Pro Zynq-7000
Type :	Soft
Deliverables :	- Source code: VHDL Source Code or/and VERILOG Source Code or/and FPGA Netlist - VHDL & VERILOG test bench environment: Active HDL automatic simulation macros, ModelSim automatic simulation macros, NCSim automatic simulation macros, Tests with reference responses - Technical documentation: Installation notes, HDL core specification, Datasheet - Synthesis scripts - Example application - Technical support: IP Core implementation support, 3 months maintenance, Delivery the IP Core updates, minor and major versions changes, Delivery the documentation updates, Phone & email support