EDACafe.com - Intellectual Property : Virage Logic Corporation -


Short Desc. :	INTELLI™ DDR2/DDR3 1600Mbps PHY+DLL FOR HIGH-PERFORMANCE DRAM MEMORY CONTROLLERS
Overview :
Virage Logic’s Application Specific IP (ASIP) Intelli DDR2/3 PHY+DLL is a fully digital, flexible and advanced solution for ASIC and SoC designers who need to get the ultimate performance out of their memory interface using the least amount of silicon area. The Intelli DDR2/3 PHY+DLL is ideal for applications that need to initially support DDR2 devices, but require the flexibility to support DDR3 devices as their price/performance advantages emerge.
Features :	- Backwards compatible with the DDR2 standard and supports all DDR2 features - Complete DDR3 support including read leveling and write leveling - Fully digital design - Up to 800MHz clock speed (1600 Mbps/pin data rate) in 65nm process and smaller - Standard cell based DLL - Clean partitioning between scheduler and PHY allowing easy mix-and-match of controller and PHY from Ingot, customer, or third party - Support for every imaginable combination of data bus width, DRAM density, and 1 to 4 ranks - Low-power features such as powering down pads and disabling data capture on individual bytes with read data mask bits - DQS squelch that automatically matches pad and board trace latencies - “read data valid” indicator to core logic using programmable timing for minimum latency or calculated timing for maximum flexibility
Categories :	Memory
Portability :	ASIC SOC
Type :	Soft