All Categories : Technical Papers : Synopsys Papers Bookmark and Share

Title : Reduce Power, Area and Routing Congestion - Analysis of a High-Performance On-Chip-Bus Interconnect
Company : Synopsys Inc.
Date : 03-Feb-2010
Rating :
Downloads : 48

Rate This File
5 Stars
4 Stars
3 Stars
2 Stars
1 Star

This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare® Interconnect Fabric for the ARM® AMBA® 3 AXI™ while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare Interconnect Fabric used to meet the stringent timing requirements. Detailed technical analysis is provided for the selected architecture, pipelining mode, arbitration scheme and the slave visibility feature employed to reach timing closure for the links with demanding performance requirements. Final results are presented based on the hybrid architecture of the DesignWare Interconnect Fabric used to optimize the infrastructure resulting in a reduction in area, power and routing congestion.
User Reviews More Reviews Review This File
Featured Video
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Ansys’ John Lee on Cultivating Trust within his Team
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
The Role of the Portable Stimulus Standard in VLSI Development
Jobs
Hardware Development Engineer - (PCB) for Cisco Systems Inc at Austin, Texas
RF Design Engineer for Blockwork IT at San Francisco, California
Advanced Mechanical Engineer for General Dynamics Mission Systems at Marion, Virginia
Senior Staff Engineer for Samsung Electronics at San Jose, California
Physical Design Engineer (Multiple Openings) for Samsung Electronics at Austin, Texas
Senior SOC Design Engineer for Nvidia at Santa Clara, California
Upcoming Events
SEMICON Southeast Asia 2024 at MITEC Kuala Lumpur Malaysia - May 28 - 30, 2024
3D & Systems Summit - Heterogeneous Systems for the Intelligently Connected Era at Hilton Dresden Hotel An der Frauenkirche 5, 01067 Dresden Germany - Jun 12 - 14, 2024
2024 IEEE Symposium on VLSI Technology & Circuits at HILTON HAWAIIAN VILLAGE HONOLULU HI - Jun 16 - 20, 2024
Design Automation Conference (DAC) 2024 at Moscone West, San Francisco CA - Jun 23 - 27, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise