Because as much as you and I know that technologists are so interested in DFM, they lay awake at night pondering the difficult physics and engineering of designing things to be supremely manufacturable, what really adds merit and oomph to all of their native curiosity and insomnia is, "Yeah, and can I make money on the solutions I come up with? And will I beat everybody else to the punch?"
This column started back in February at DesignCon in Santa Clara. Canaccord Adams hosted a panel called, "The Business of DFM." The panel was moderated by Dennis Wassung, and the panelists included Riko Radojcic from Qualcomm, Ed Wan from TSMC, Jean-Marie Brunet from Mentor Graphics, Jim Wiley from Brion Technologies, Thomas Blaisi from SIGMA-C, and Yervant Zorian from Virage Logic. The questions under discussion here in EDA Weekly arose from that February panel, and include responses from three of the six panelists, plus Mentor Graphics' Joe Sawicki subbing for Jean-Marie Brunet.
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One of Joe's slides attempted to lay out the current landscape of DFM -- at least from Mentor Graphics' point of view -- so I decided to expand the scope of this column by submitting my questions to all 14 companies on Joe's slide. I heard back from 10 of them, plus a few other companies as well.
So, go get that tall, extra hot, non-fat, with-whip, grande, double-shot, white mocha. This column -- this "virtual panel" on the business of DFM -- is (groan) over 9000 words long and includes feedback from 15 different companies. The “panelists” include:
Jacob Jacobsson, CEO, Blaze DFM
Atul Sharan, President and CEO, Clear Shape
Chenmin Hu, President, Anchor Semiconductor
Dale Pollek, President & CEO, ChipMD
David Thon, Group Product Marketing Director, DFM, Cadence Design Systems
Dwayne Burek, Senior Director, Design Implementation, Magma Design
Joe Sawicki, Vice President & GM, Design-to-Silicon Division, Mentor Graphics
Mike Gianfagna, President & CEO, Aprio Technologies
Naeem Zafar, President & CEO, Pyxis Technology
Nitin Deo, Sr. Vice President, Marketing & Business Development, Ponte Solutions
Riko Radojcic, Leader of the DFM Initiative, Qualcomm
Rob Aitken, ARM Fellow, ARM
Thomas Blaesi, VP of Marketing & Business Development, SIGMA-C
Srinivas Raghvendra, Senior Director of DFM Solutions, Synopsys
Won-Young Jung, CTO & Executive Vice President, Nanno SOLUTIONS
Yervant Zorian, Vice President & Chief Scientist, Virage Logic
When you're done reading and if you find yourself completely addicted to this stuff (the business of DFM, not caffeine), this is your lucky month! Because there's more where this came from in the shape of a panel happening during the last hour of the last day of the Design Automation Conference in San Francisco, “DFM: Where's the Proof of Value?”
Per the organizers: “The aim of this DAC panel is to provide a serious comparison of related DFM technologies on the market and some idea of the cost and difficulty of integrating the tools into a fixed design budget and timeline. Specific results will be cited, along with examples of expected ROI (monetary, quality, reduced time-to-market, and comprehensive yield enhancement). The audience should walk away with enough information to make an informed decision on which companies would make sense for their DFM challenges, to reach their own yield and throughput goals.”
The moderator is Joe Brandenburg, and the panelists include Jacob Jacobsson, Atul Sharan, Joe Sawicki, Naeem Zafar, and Synopsys' Raul Camposano. This promises to be a fascinating hour and an appropriate end-point for DAC 2006. You should plan to attend. It's happening at 4:30 PM on Thursday, July 27th. Hope to see you there!
[Editor's note: If you weren't included in the (thanks to “EDA John”) now-infamous Buzz@DAC.2006 Part 1 here in EDA Weekly , please send me your or your company's 100-word commentary on what you think will be hot at DAC in San Francisco. I need to hear from you by July 12, 2006.]
The Business of DFM …
1) If you're making money in the DFM market, briefly tell me what technology you're selling. Please be succinct. I'm easily confused here (not kidding!).
Jacob Jacobsson, Blaze DFM -- Blaze is receiving orders for our initial “Electrical DFM” product -- Blaze MO. Blaze MO which was announced in May and is available today as a production release, transforms power and timing requirements into manufacturing directives that optimize the manufacturing process for each individual design. The main benefits are lower leakage power and leakage variability resulting in substantial double-digit gains in parametric yield.
Atul Sharan, Clear Shape -- Clear Shape provides technology that accounts for the impact of systematic variation on design. What designers draw and model -- the ideal -- is NOT what is seen on silicon at sub-100 nanometers. These systematic variations are predictable, and the impact is large enough to cause catastrophic failures such as opens and shorts, also called yield "hot spots." Addressing systematic variations requires too many new rules for rule-based DRC to be sufficient on its own. Additionally, post-GDSII OPC is too slow and occurs too late in the process to be useful to designers.
Clear Shape provides model-based DFM tools which have the requisite speed and accuracy to allow designers to identify manufacturing problems up front in the design cycle -- for example, yield hot spots and impact on electrical parameters such as timing, signal integrity and leakage power -- so that they can do silicon-accurate designs and get the maximum from their process.
Chenmin Hu, Anchor Semiconductor -- As an early start-up in DFM, Anchor has made significant revenue. The first paid customer of Anchor was Xilinx, a fabless design company. That was more than three years ago. The technology is mainly in Lithography Process Check to identify potential hot spots in layout designs.
Dale Pollek, ChipMD -- We provide circuit design (Spice-simulation based) analyses and diagnoses for interactive and automatic circuit optimization of performance and yield. In street terms that means: DesignMD automates tasks, provides a lot more circuit knowledge in less time to make the engineer a lot more intelligent so the designer can make smarter decisions (or use automated decisions as desired) in less time to market netting much better (more robust) circuits (i.e., less time to more market share and profits).
We provide one of the only “design for” solutions that is literally aimed at the high-cost/risk engineer level “design” stage of the flow. Not post layout tooling or drafting stuff that certainly helps make a design to improve manufacturability, that stuff certainly is important, but there is just not really much “designing” at that stage anymore, is there? Most of what I've seen called DFM should really be categorized as LIMA -- Layout, Implementation, Manufacturing, or Autopsy of dead silicon.
David Thon, Cadence Design Systems -- Cadence supplies a broad range of advanced physical verification, extraction, analysis, and RET solutions serving the DFM market segment. These solutions include Assura, Diva, Dracula, Cadence Physical Verification System, Cadence QRC Extraction, VoltageStorm, the Virtuoso RET Suite, Cadence Chip Optimizer and others.
Dwayne Burek, Magma Design Automation - Magma provides a complete RTL-to-GDSII implementation system. This is complemented with a model-characterization environment and physical-verification system. Magma can really provide a full solution from characterization to physical verification sign-off.
DFM is definitely an essential component to the complete solution. As Such, some DFM-related technology is bundled within our implementation solution while some of the advanced DFM capabilities are sold separately. Magma has two products on the implementation side that address DFM: Blast Yield, a generic DFM solution, and Blast Yield TX, a TSMC 65-nanometer specific DFM solution.
The pull from customers really depends somewhat on their process node plans. Those at 90 nanometers with plans to transition shortly to 65 nanometers, are more focused on qualifying the 65-nanometer solution and are comfortable with their current 90-nanometer solution. Those that plan to continue to use 90-nanometers for some time, are more interested in having a solution for that node. Thus, the urgency for solutions is really split, since at 65-nanometers, DFM will be a requirement -- at 90 nanometers, it is somewhat a nice-to-have unless all your high-volume business is centered there and any yield improvements translate directly to the bottom-line.
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Mike Gianfagna, Aprio Technologies -- Aprio sells both design and manufacturing tools. We believe you need core competency in both markets to make a real contribution to DFM. On the manufacturing side, we sell litho-repair tools and OPC tools. On the design side, we sell a tool that quickly and accurately predicts what a layout will look like when printed in silicon. We only provide the data here -- we work with existing tool providers to integrate this data to provide the end-user benefit.
Naeem Zafar, Pyxis Technology -- We are not making money yet, but we intend to later this year.
Nitin Deo, Ponte Solutions -- Ponte has been selling Yield Analyzer for analysis of libraries, memories, and full-chip designs at 130 nanometers, 90 nanometers and 65 nanometers. This model-based analysis includes defect-limited-yield issues that are highly design dependent and cannot be detected by traditional DRC tools or any rule-based tools like P&R. With 4 out of the 5 largest foundries endorsing Ponte's accuracy, designers are beginning to use our tools for analysis as well as verification. Now is prime time for yield!
Riko Radojcic, Qualcomm -- We are an end user of DFM technologies, and surely expect to make money from it -- through faster ramps and better yields. In the short term, we expect to use shape simulators (for litho/etch effects), critical area simulators (for defectivity analyses), thickness simulators (for CMP effects), and tools that help optimize leakages through design-driven OPC.
Srinivas Raghvendra, Synopsys -- We think of DFM tools as those that are involved in tapeout and post-tapeout activities. Tools such as Proteus OPC, CATS MDP, SiVL LRC, Test chips and Odyssey Yield Management Software are part of our DFM portfolio.
Thomas Blaesi, SIGMA-C -- We sell lithography simulation and our customers are semiconductor companies, fabless and IDMs, and foundries. Our product is used primarily for process development and, more and more, lithography simulation also is required in the post-OPC signoff flow to verify the OPC patterns and to make sure designs are litho-friendly and yield well.
Won-Young Jung, Nanno SOLUTIONS -- Our product is a process-aware statistical worst-case modeler for interconnects.
Yervant Zorian, Virage Logic -- Yes, we do make money out of DFM, but not by selling a stand-alone DFM offering, rather by integrating DFM solutions into our products. Virage Logic as an IP provider that not only uses DFM tools and methodology while designing its physical IP, but also builds into the same IP the necessary manufacturability for the IP to repair itself upon manufacturing and result in optimal yield -- this is know in the industry as "silicon-aware" IP. The price of our Silicon-aware IP includes the capability of our products to test and repair themselves.
2) Has the skepticism over DFM subsided a bit over the last 18 months as far as being a revenue-generating business opportunity -- in other words, are DFM vendors silencing their critics by actually making some money?
Jacob Jacobsson, Blaze DFM -- Companies that are targeting yesterday's hot technologies, such as OPC/RET, have an uphill climb due to the dominance of the two market leaders in those technologies. Those of us that have been able to identify different needs that are growing in importance, but that are still woefully under-served, such as the rising importance of leakage power and variability below 100 nanometers, will continue to do very well.
Atul Sharan, Clear Shape -- My personal bet is that DFM, though a newer technology area, will easily surpass ESL in revenue by end of 2007 - if not before - and remember RET/OPC is NOT DFM revenue. As for a preview of which EDA vendors will make money … the designers and the foundries have already started speaking out as to which companies are actually solving their DFM problems in a useful manner.
Chenmin Hu, Anchor Semiconductor -- Anchor has paying customers including design companies, foundries and IDMs, with multiple over-million-dollar accounts. The difficulties in revenue generation have been mainly due to the lack of process data availability to both the design community and DFM venders. Anchor is the only DFM start-up providing solutions to both IC manufacturers and designers. It has enabled Anchor so far to generate more revenue from foundries and IDMs than fabless companies. TSMC starts to make its process data available for its customers in DFM applications. Significant DFM revenue generation from design companies is expected starting from Q4 this year.
Dale Pollek, ChipMD -- In our specific niche, there has not been as much a problem with skepticism but it has mostly been the very poor situation of lack of budgets for ANY EDA tools for the last three to four years as the EDAC and Dataquest numbers confirm. BUT, 2006 definitely is showing good growth opportunities and optimism of many more companies engaging with us.
To your last point, yes, deals are happening and improving more recently, but it seems this is mostly due to the entire market recovering and starting to really do new designs. There is a small portion of the cause being helping educate the user base to get past the really bad experiences they had from the first two generations of attempting to provide circuit optimization and analog automation tools. Maybe the most important reason is that more companies are now experiencing the problems of nanometer processes and venturing into the next smaller level of IC Process that they now know they must find a solution like ours.
It is nice to note here that at ISSCC earlier this year, an IBM technical expert commented that the old methods will not work and that only the worst-case approach can address this (DesignMD is the only commercial implementation of WC technology). So, as the word is getting out, more are becoming informed, and this is getting them excited/concerned and therefore engaging with us.
David Thon, Cadence Design Systems -- We don't believe there's that much skepticism about the business opportunity for DFM. Major EDA vendors have been successful for years in this market segment.
Dwayne Burek, Magma Design Automation - No. Most revenue today is being made by vendors selling tools like OPC to the fabs. Otherwise, customers tend to view DFM as a necessary feature in existing tools (e.g., P&R and DRC) to support 65 nanometers. This is why Magma has tried to separate out the advanced DFM features from those that are the necessary features in any P&R and DRC tool.
To be successful, the benefits in terms of yield improvement need to be measurable otherwise the extra revenue generation can only be associated with faster turn-around-time or easier to use tools and flows. So, standalone vendors selling "DFM signoff" or "DFM optimization" tools have a big challenge ahead of them.
Joe Sawicki, Mentor Graphics -- Although John Cooley says my predictions for growth in the DFM market are wrong, there is “real stuff” in this market and real buzz around what's happening in the start-ups. All types of DFM tools - design focused, manufacturing for design, and “old school” tools like DRC, parasitic extraction, and physical analysis - were generating over $500 million by 2004. I believe that market will surpass $1 billion by 2008, and $1.5 billion by 2010. Over 80 percent of today's market is owned by Mentor, Synopsys, and Cadence, while Mentor has a 40-percent market share in the market we serve [which excludes TCAD and yield ramp]. [Comments paraphrased from my phone call with Joe Sawicki.]
Mike Gianfagna, Aprio Technologies -- Not yet. There is a difference between the evaluation phase and production phase. For the most part we're still in the eval or testing phase. Full-production deployment will tell the real story, and that's ahead of us.
Naeem Zafar, Pyxis Technology -- Absolutely! In our case, the value proposition is clear and has economic value. And, we see our partners making money already
Nitin Deo, Ponte Solutions -- Yes, at least Ponte is. We are providing real value that open designers' eyes to previously unknown problems and they can do something about those problems with trade-off between yield and area or yield and timing.
Srinivas Raghvendra, Synopsys -- We can't speak for the other DFM vendors, but Synopsys has a very healthy and growing DFM business.
Thomas Blaesi, SIGMA-C -- SIGMA-C absolutely sees DFM as a viable moneymaker for this industry. It's a major requirement at 65-nanometer nodes, and essential below that. There are point-solutions making money, but the main challenge is creating integrated DFM solutions throughout the design flow.
Won-Young Jung, Nanno SOLUTIONS -- Yes, it has.
Yervant Zorian, Virage Logic -- We are seeing more and more interest in DFM, particularly with the move during the last 18 months from 90 nanometers to 65 and 45 nanometers, and as the impact of random and systematic defects in silicon is increasing. That is why we feel it is more and more important to put the DFM right into the IP. Defect density is increasing, as well, and the need for DFM increases with it. Today's chips at 65 nanometers are being manufactured at a much higher volume, because most of them are targeting consumer electronics -- cell phones, games, and so on. For these high-volume chips, DFM and thus higher yields are very critical. If some company revenue relates to DFM and yield, then these large volumes on the 65 and 45 nanometers will definitely increase such revenue.
3) If OPC/RET and wire spreading have been around for a while, what is the 'new' part of DFM that seems to be generating so much interest?
Jacob Jacobsson, Blaze DFM -- At Blaze, we believe that “Electrical DFM” is the next wellspring of growth, not just for DFM, but for all of EDA. Today, there is so much valuable information, on both sides, that is not being put to good use. There is a lot of manufacturing information that is available in standard design kits that is going to waste on the design side, and there is a wealth of power and timing information that is not being put to good use on the manufacturing side. Since electrical DFM solutions are fully aware of the power and timing requirements of the design, they optimize the design based on manufacturing information and then optimize manufacturing based on design requirements.
Atul Sharan, Clear Shape -- OPC/RET are lithography post-GDS-II solutions, meaning they occur too late to help the designer during design. Wire spreading addresses random manufacturing variations--opens and shorts caused by random particles on the mask. However, at sub-100 nanometers, the biggest DFM issue is systematic variation -- highly predictable variations in shape caused, in great part, by the fact that the lithography wavelengths are now far bigger than the process geometries.
Chenmin Hu, Anchor Semiconductor -- The IC manufacturing process is actually a pattern-transfer process from layout design to mask, wafer, etc. In advanced nanometer technologies, the final patterns on the wafer are very different compared with the original layout designs. Most yield problems, including performance related yield problems, come from pattern transfer. Clear understanding of properties or characteristics of patterns can be a very important 'new' part of DFM.
Dale Pollek, ChipMD -- Peggy, “where's the D” here? I sound like that ancient Wendy's commercial of “where's the beef,” but please help the world understand how anything done at and after layout is considered D, unless the D in DFM is for “Drafting?” Sure, some of the characteristics of the drafting, tooling and manufacturing stages require designers to input and assess the impacts to help make decisions, but that is definitely more “dealing with manufacturability” and not “designing for manufacturing.” Isn't it?
David Thon, Cadence Design Systems -- It's becoming more important that manufacturing effects are modeled within the design flow as design is being done -- rather than remedied in post-processing operations -- so the design will be manufacturable with reasonable yield when it gets to the fab. These manufacturing effects include lithography, CMP, etch, thermal, and others.
Dwayne Burek, Magma Design Automation - There are two answers: a) adding lithography (OPC/RET) awareness into the complete design flow, including P&R, analysis, and DRC. This is important for 65 nanometers, necessary for 45 nanometers; b) TSMC and other foundries are now making DFM information available to their customers.
Mike Gianfagna, Aprio Technologies -- These two applications are parts of a comprehensive solution. You need more applications than just these two, and you need a lot of good integration work to make a real solution. Those pieces form the "new" part.
Naeem Zafar, Pyxis Technology -- That was so 5 years ago! It was the 1st-generation of DFM tools that merely helped fab and mask people -- designers did not even feel it (like a 4.1 earthquake). Then came the 2nd-generation tools, (in 2005 and 2006) where some post-layout changes were done based on DFM analysis. There are examples [in this generation of tools] from Cadence's Catena, Sagantec's DFM-Fix, etc. There was also buzz, as various DFM companies brought out DFM analysis tools for various types of yield problems. Now, in the future, you will see the 3rd-generation DFM tools that promote correct-for-manufacturing designs (both in libraries and wires -- as in routing).
Nitin Deo, Ponte Solutions -- Quantification of those issues. It's like this -- people have known for years that sugar and caffeine are bad for health, but now technology can exactly quantify it for you and also tell you individually what is bad for you given your own health. Similarly, now these technologies are becoming very design-specific -- which is absolutely critical for steady and high yield.
Riko Radojcic, Qualcomm -- The 'new' bit vis-à-vis RET is that there are now tools aimed at designers to help make layouts more RET-friendly. The 'new' bit vis-à-vis wire spreading is that there are now tools that can simulate and quantify the yield benefit of wire spreading.
Rob Aitken, ARM -- Historically, DFM has been considered a post-tapeout activity. OPC/RET has been used for a long time, but it is being used on more layers with each process generation. The current wave of interest in DFM began with the realization that making the pre-tapeout design more OPC friendly would result in a better optimization between performance, area, and yield. However, it's one thing to say that DFM should be more a part of design, and quite another to figure out exactly how that happens. DFM can potentially interact everywhere from library creation through synthesis, place and route, extraction, DRC, and DFT. The challenge has been determining the best place for DFM, from both a technical and business perspective. Many approaches have been proposed, but only some of them will succeed.
Srinivas Raghvendra, Synopsys -- Designers are seeking tools that help them accelerate time to yield. With foundries such as TSMC announcing the availability of DFM data for designers, we expect this to be an interesting and growing segment of the DFM market.
Thomas Blaesi, SIGMA-C -- It's all about yield. At 65 nanometers, lithography-related yield issues are becoming more and more prevalent. Maximizing yield is a key effort especially for high-volume designs. Designing with all the necessary margin to meet all the design rules makes it almost impossible to achieve the performance targets (area, speed, and power consumption) of a design. Therefore, an iterative Design-for-Manufacturing methodology is required, including a whole set of DFM implementation and verification tools to make sure any given design can be optimized for yield.
Won-Young Jung, Nanno SOLUTIONS -- OPC/RET and wire spreading are not new; it's just the new interfaces to the existing design flows which are important.
Yervant Zorian, Virage Logic -- OPC/RET and wire spreading are important solutions, but they are only a part of the total DFM on-chip. Their impact is on the design and lithography optimization stage. Other critical DFM capabilities and resulting yield improvement can be performed at the back-end manufacturing stage, such as during wafer sort, repair, packaging, final test, and silicon debug.
4) Why did Numerical Technologies get acquired by Synopsys? Why wasn't there enough of a market to offer an opportunity to IPO, or at least to stay an independent entity?
Jacob Jacobsson, Blaze DFM -- We don't have any insight into Synopsys' motivation for purchasing Numerical.
Atul Sharan, Clear Shape -- Numerical did an IPO. They were acquired by Synopsys because they could not overcome their CEO-transition issues and the Board -- as is often the case -- may have lost patience at the wrong time. Indeed, Numerical should still have been a stand-alone company. It was, however, a great move by Synopsys as it completely locked out Cadence from having any meaningful OPC/RET solutions and consolidated a lot of the technical lithography expertise at Synopsys -- at least for a few months…
Dale Pollek, ChipMD -- No specific comment on Numerical … but please note there are a lot of companies that have left the earth or been acquired for pennies on the dollars invested -- and this is across all of EDA, not just in DFM. That is also something NOT NEW in EDA that I have known for over two decades. Just consider it the Darwin Theory of EDA, the select few survive and thrive, even in the worst of market conditions.
Also, some (I do not know if this applies to NT) of those in EDA who did “bail out” were just “too early.” In the 25 years I've been involved with EDA, I've seen many companies just not get enough traction in a short enough timeframe, because the users were able to fend off the problem just long enough for them. Often, it was the next vendor who came in with a new product (sometimes using the original assets) at the time the market finally really needed a solution.
David Thon, Cadence Design Systems -- Synopsys and Numerical Technologies are probably best positioned to respond to this line of inquiry, but in any case we believe this acquisition reflected the need to bring more DFM into the traditional design flow as mentioned above.
Dwayne Burek, Magma Design Automation - There could be several factors not necessarily related to a company's viability as a stand-alone entity. Certainly there is a trend to provide more complete solutions and the major EDA vendors need to either acquire or develop DFM technology.
Mike Gianfagna, Aprio Technologies -- Can't say; I wasn't involved in the deal. As I recall, Numerical was public before the acquisition, however. (Traded on the NASDAQ as NMTC.)
Naeem Zafar, Pyxis Technology -- Numerical DID have an IPO. Synopsys saw the strategic value and paid a premium. But there were other companies that brought our similar and newer technologies. And, the technical founders of Numerical are now at new DFM start-ups.
Srinivas Raghvendra, Synopsys -- Numerical had technologies in RET, PSM and CATS, the mask data preparation (MDP) tool, which were complementary to Synopsys' design strengths. The combination of Synopsys and Numerical gave us a very strong position in DFM. In general, we believe that for DFM solutions to be effective, they need to be part of a larger, more comprehensive solution.
Yervant Zorian, Virage Logic -- I would make your question more general by asking, is a company that offers only DFM solutions today going to survive as a stand-alone company, or is DFM better if incorporated into an integrated tool flow or IP? My answer would be that, it is natural to have point tool solution providers today, at this early stage. But, over time, these solutions will need to be migrated into integrated solutions. I think, most of today's DFM start-ups will end up like Numerical Technologies.
5) Is DFM still in the 'educational' phase, both with respect to engineers and the VC community?
Jacob Jacobsson, Blaze DFM -- There are always new things that we can learn, especially during and right after a transition to a new process node. So, in that sense, we'll always be in education mode. However, we believe that it is fairly well understood that the first DFM tools were all geometric, or “shape-centric”. The currently emerging solutions are “design-centric” in that they understand the power and timing requirements and know how to use those requirements on the manufacturing side. As far as VCs, they seem to understand that there is not much financial opportunity in backing geometric DFM tools, but that there is significant upside potential in electrical DFM solutions.
Atul Sharan, Clear Shape -- DFM is 'evolving', and like everything else in the semiconductor industry, new technology solving real problems takes one generation longer than what is first predicted.
Dale Pollek, ChipMD -- Yes, DFM still has a lot of education going on and always will, in other niches of DFM than what ChipMD/MunEDA [Munich-based EDA partner of ChipMD] is involved in. It's due to many variables and many new, emerging ideas and technologies. In our specific DFY (Design For Yield) niche of DFM, the education process we are spending our efforts on during pre-sales is mostly helping the designers “recover” from the really bad experiences of the prior attempts to provide circuit-level automation and optimization, since they mostly failed miserably at best.
Now that we have multiple companies on public record of achieving great successes, we are turning that corner from skepticism to more of a perspective of “tell me more” and “let me prove it to myself.” Still and always, however, there will be some “education.” But in our case, it is now shifting more to that of helping the rest catch up to the leaders in the industry who have already proven how well DesignMD works.
David Thon, Cadence Design Systems -- There will always be an educational flavor to the leading-edge concepts in DFM, but the general notion of DFM is widely accepted, and represents a major market segment today.
Dwayne Burek, Magma Design Automation - There will continue to be an educational and learning aspect to DFM since new process nodes are introducing either new manufacturing issues or exasperating current limitations. What is important is that there are real problems and real solutions being worked on or being deployed.
Joe Sawicki, Mentor Graphics -- DFM is complex, but some of us have been working in this area for many years. We are beyond the 'educational' phase. [Comments paraphrased from my phone call with Joe Sawicki.]
Mike Gianfagna, Aprio Technologies -- For engineers, yes. They are kicking tires a lot. For VCs, no. They have chosen the approaches they like and placed their bets.
Naeem Zafar, Pyxis Technology -- To some degree, yes -- but this is an evolutionary process. They are a lot more educated than they were 3 years ago, or even 1 year ago. One has to educate oneself as problems begin to hit us all in the face. Now, designers and customers do not have to be sold on the benefit of DFM (largely speaking).
Nitin Deo, Ponte Solutions -- Yes, but that is expected. I think it will take at least a year before engineers start using these tools as part of their job and then the information trickles down to VCs. We got the first indication of that just two weeks ago when a potential customer called us on his own and now we are in the process of setting up the complete flow for his design team.
Riko Radojcic, Qualcomm -- There is no doubt that DFM is still in a 'missionary sell' phase of adoption. The big barrier last year was access to the appropriate process data necessary to make the DFM simulators work. That barrier has been overcome, as per the recent announcements from all major foundries. However, there are still significant barriers to be overcome before DFM, under its current definition, becomes mainstream technology. The barriers are now more on the user side, and the principle challenges are associated with integration into the design flows. In addition, the value proposition from these tools is still anecdotal and qualitative, making conventional ROI analysis hard to do.
Rob Aitken, ARM -- I would describe it as a learning phase, and I think we are beginning to emerge from it. For example, designing layout that is robust in the presence of lithography variation requires some understanding of the manufacturing process. The first tools in this space required explicit, detailed descriptions of every aspect of a process recipe, and understandably foundries were generally unwilling to provide these. Instead, they offered DFM recommendations in the DRC decks, which helped yield, but at the expense of over-constrained design.
ARM spent the last couple of years working with the foundries to develop metrics and methods that identified lithographically important issues in a more efficient manner than a DFM deck, but without requiring detailed process information. This resulted in high quality physical IP at 90 nanometers and 65 nanometers. The upcoming generation of lithography simulation tools is now using encrypted process data and going forward will enable even better interaction between design and manufacturing without compromising the secrets of either.
Srinivas Raghvendra, Synopsys -- Designers who are at the 65-nanometer node are asking for DFM solutions, so it's clear that we are no longer in the evangelism mode.
Thomas Blaesi, SIGMA-C -- Yes, to some extent, because of its complexity.
Won-Young Jung, Nanno SOLUTIONS -- Yes!
Yervant Zorian, Virage Logic -- I think you are asking if I had some money to invest in a DFM company, or to buy a DFM solution, what would I do? How would I choose the best among many? First, I need to find out which DFM product, and thus which company, results in the highest yield. DFM solutions today definitely differ from each other. Some solutions have minor yield improvements versus others, such as Virage's silicon-aware IP, which provide total self-repair that often increases the yield as much as 200 percent. So, I would put my money where I see the greatest increase in yield. Whether to buy or invest, is something I would have to examine on a case-by-case basis.
6) If you had $10 million tomorrow from an investor, how would you spend it enhancing your DFM offerings, or what additional tools would you buy from your DFM vendor, if you're a user?
Jacob Jacobsson, Blaze DFM -- Because of the importance of leakage power and variability, we believe that our product offers substantial benefits to the vast majority of engineers designing chips with sub-100 nanometer process technologies. Given that, the best use of the money would be to expand our sales, distribution, and support networks to get our products into their hands as quickly as possible.
Atul Sharan, Clear Shape -- If Clear Shape got an extra $10M, we would expand our R & D and Applications to better penetrate and serve customers.
Dale Pollek, ChipMD -- Deployment or call it “Channel.” With the hundreds of silicon-proven design successes of DesignMD now, and hundreds of users on all three major continents of EDA users (Europe, Asia and U.S.), the only limit to our growth will be adding enough pre-sales support, sales and marketing staff. We are growing now based on profits of our sales successes, so extra cash invested would be able to return on itself very quickly. For us, it is now a safe-bet opportunity for investors.
David Thon, Cadence Design Systems -- We'd continue to invest in developing manufacturing models that are crucial to a manufacturing-aware design flow.
Dwayne Burek, Magma Design Automation - Probably one of the biggest limits to more wide-spread adoption is being able to provide IDM or foundry-specific solutions. So, this is not necessarily a lack of technology, but more of a resource bandwidth situation -- investing in additional resources to come up with a more scalable infrastructure for foundries and IDM's to pass manufacturing-related data and models to the implementation and verification tools, and for implementation tools to pass more design intent to manufacturing is where we need help.
Mike Gianfagna, Aprio Technologies -- I would hire a lot more AEs and QA staff. These two job descriptions, more than any other, enhance the customer experience.
Naeem Zafar, Pyxis Technology -- We just got our $10M last week, so we are planning the answer to this question even as we speak. But, tighter interconnection between the DFM analysis tools and design implementation tools is the future (just like timing and routing were in 2000 and 2001).
Nitin Deo, Ponte Solutions -- If we had $10 million, we would build a solid platform to address all yield-related issues (i.e., random defects, systematic defects, lithography issues) for all design styles (libraries, memories, full chips, etc.). This platform should be able to adapt our own models, as well as anyone else's models for such process phenomena. Today, all DFM suppliers are addressing only one or two aspects of the whole yield issue. That's not going to work for too long.
Rob Aitken, ARM -- Now that the conventional lithography-centric DFM/DFY space is reasonably well covered by commercial tools, the next DFx challenge is design for variability. Example applications include statistical timing, design centering, and circuit tuning. These approaches take manufacturability as a starting point, which means a variability window in practice, and then look at optimizing the design to either use the variability to benefit performance or power, or quantifying the variability in order to locate a design point that minimizes its effects.
Thomas Blaesi, SIGMA-C -- Unlike the electrical side, where SPICE is the standard model to describe the transistor, currently, there is no standard process model that can be utilized by a series of tools in a DFM flow. Creating this would put the money to good use.
7) Are the in-house DFM tools really the majority of those being used today ... i.e., is there really a market in the EDA space for vendors other than the big 3 or 4 who have the channel and the R&D budgets to pursue expensive advancements in this highly technical area?
Jacob Jacobsson, Blaze DFM -- As we mentioned before, there is a lot of useful manufacturing information in a standard design kit that is going to waste on the design side. There is a lot of useful design information that is not being put to good use on the manufacturing side. There are a lot of obvious things that should be done that aren't being done. But, it takes a good understanding of both design and manufacturing to be able to recognize these things. That's been one of the problems. Chip designers don't recognize useful manufacturing information and manufacturing engineers don't recognize useful design information. Electrical DFM solutions are infused with knowledge of both worlds and recognize how to transfer that information from each side to the other in a way that is useful to both.
Atul Sharan, Clear Shape -- We do not run into any in-house DFM tools. Almost all innovation in the last 10+ years has come from start-ups. ALL of Synopsys and Mentor's OPC/RET and DFM offerings have their basis in acquired technology.
Chenmin Hu, Anchor Semiconductor -- I believe there are no easy-to-use and efficient in-house DFM tools. Historically, larger EDA venders have been mostly unable to develop highly technical products such as the DFM tools. Due to the close connection to manufacturing, the top equipment venders may also play critical role. The DFM market will not be limited in existing EDA space.
Dale Pollek, ChipMD -- Yes, as long as EDA startups stay focused on what over 20 years of history has proven -- deliver new, superior technologies that address current or now-emerging needs. There is always room for growth regardless of channel and marketing Sure, the big three (I have respect for Magma in that they sell value and not just via bundles, FAM's and discounts) have made it hard for small companies to compete on pricing of similar or like solutions -- including actions that have resulted or at least encouraged customers to delay decisions to try new solutions from startup companies.
But that is just a normal part of our market evolution, like Walmart is for retail -- commodities will keep coming down in price, while those customers are just looking to deal with keeping spending reduced, but the commodity sources cannot afford to invest to make anything significantly new. Besides, if the pricing keeps going down (EDA used to be a much bigger percentage of semiconductor market), then who can afford to build the next solution the user needs? Maybe the semi industry needs to be a bit careful here, but fortunately, we know of enough smart ones in the semi industry who understand this and are willing to work with us, so I am bullish on DFM and our company. We will do just fine and our customers will do even better.
David Thon, Cadence Design Systems -- We believe that in the long run, major customers prefer to buy advanced, reliable, commercially-supported tools from suppliers with a full range of design solutions.
Dwayne Burek, Magma Design Automation -- Only big design flows (e.g.; Magma) make sense for DFM. Point-tool solutions for CAA, CMP, and LPC, are okay for initial investigation, but do not provide value to the designers. In the end "DFM" for designers will be a check-box item for everyone's 65/45-nanometer solutions. Other traditional metrics will be what decides a customer's tool choice for physical design, physical verification.
It's important to note that you have to account for all effects in the DFM design flow -- not just CAA, CMP or litho, but also statistical variation. Statistical timing and statistical power analysis are necessary, as is design/optimization driven by this. So you need to model systematic effects (like CMP and litho), and random/statistical effects to provide a real solution.
There will continue to be a strong market for OPC tools used by the fabs, but the incumbents are being replaced by a new wave of hardware-assisted tools. Selling a "box" to the fabs makes a lot of sense; it fits nicely with their model of buying fab equipment. Plus these new boxes outperform traditional software only solutions in terms of accuracy and TAT.
Joe Sawicki, Mentor Graphics -- Many of the new players in EDA have pitched their story to me by telling me that DFM is going to be a billion-dollar industry, and they're going to get their share. That's not reality because Mentor, Synopsys, and Cadence already own so much of that market. The average revenue associated with an IPO is $21 million. I don't see too many of the current DFM start-ups ever reaching that point. [Comments paraphrased from my phone call with Joe Sawicki.]
Mike Gianfagna, Aprio Technologies -- Yes, and Yes. Today, most production tools probably are built in-house at the larger IDMs. As for the future, there is *always* opportunity for innovation from small companies. When a new approach is needed, these companies have a built-in advantage over the big EDA players. That advantage is a lack of legacy code to support and quarterly EPS goals to achieve.
Naeem Zafar, Pyxis Technology -- History has answered this question for us over the last 40 years. If there is a big enough pain, people will solve it and there will be people willing to pay for this solution. Few can name the last 5 technical breakthroughs that came from the big 3 or 4 EDA vendors. What makes us think that now it will change? It won't. The rules are written in a way that makes it very hard for a large company to truly innovate.
Nitin Deo, Ponte Solutions -- Yes. Almost all IDMs, and many foundries, have their own way of dealing with the DFM issues. They have been buying services from vendors like PDF. But, for design tools -- they had their own.
I strongly believe that the EDA industry works on two engines - innovation and automation. I also believe that the big 4 EDA companies simply provide automation. Innovation comes from start-ups - not due to lack of ideas or smart people, but simply because of focus.
Riko Radojcic, Qualcomm -- Most of the current activity in this space is, in fact, not with the big 3 or 4, but with the many start-ups. As usual, nascent markets are not necessarily very attractive to the existing big entities. Having said that, it is clear that as the technology matures and it is mainstreamed, there will be considerable consolidation, and we will probably end up with a few big players.
Thomas Blaesi, SIGMA-C -- The innovative cycle in EDA requires new solutions, and DFM issues have initiated such a cycle. History has shown that semiconductor companies buy from whatever companies can best solve their design problems. Best-of-breed solutions often are provided by small innovative startups that have a single focus and apply the best resources for that single subject.
Srinivas Raghvendra, Synopsys -- There are a few very large leading-edge companies that have some internal DFM solutions, and this is completely consistent with how EDA tools have always been developed. Leading-edge companies create some internal tools, but over time move to commercial tools as they mature and as the ROI for internal tools becomes less justifiable.
Won-Young Jung, Nanno SOLUTIONS -- NO, because the current main stream technology is co-development and IP reuse in SoC design.
Yervant Zorian, Virage Logic -- I think there is space for even more DFM companies to come in. There is lots of interest and lots of need. I believe today there are 40 companies with offerings in DFM. We need all the innovation, so this is good. However, after a while, the technology will become more stable. Over the long run, after it's stable, these companies will be absorbed and there will be a consolidation in the industry. The IDMs today do have in-house tools, but they are interested in innovative solutions from third-party vendors. If there are no good tools available, if they do not see options that are of interest, they will continue to develop in-house solutions.
8) Will the next generation of designers not need to worry about DFM because they'll be working more and more on reconfigurable or programmable platforms?
Jacob Jacobsson, Blaze DFM -- We don't believe that the design world will be taken over by programmable devices. Leakage power is just as critical a consideration in programmable devices as it is in ASICs. Electrical DFM solutions dramatically reduce the leakage in ASICs, however, no corresponding solutions exist for programmable devices. So, power is a major limiting factor in this trend.
Atul Sharan, Clear Shape -- No, this won't make a dent in their DFM problems.
Chenmin Hu, Anchor Semiconductor -- Just like Xilinx, designers on reconfigurable or programmable platforms are required to be early users of most advanced technologies. They need to worry more about DFM in order to have quick yield ramp up.
Dale Pollek, ChipMD -- No, there are continued new problems arising at every IC technology node; it is just the focus that shifts. A few years back, everyone claimed to be a Signal Integrity (SI) solution, for now it seems the spin needs to include DFM even if not doing anything during the real design stage of the flow.
For example, we have recently seen a surge -- starting now -- from digital user interest at the 90-nanometer level who definitely see a need for us at the 65-nanometer node and below. Earlier, our focus was only on analog/mixed-signal, RF and then added memory design. But as designs keep going to new IC technology nodes, there will be more new issues to sort out. Some will be solved by existing tools, others need new tools and as always some will be solved by methods other than just EDA tools.
David Thon, Cadence Design Systems -- Some types of design will migrate to reconfigurable or programmable platforms, but the trend doesn't seem as strong as it did a year ago. Conversely, the trend to integrate manufacturing awareness into established design flows seems to be gaining strength.
Dwayne Burek, Magma Design Automation - Restrictive design rules and processes are one way of countering some of the effects of variability, but this will likely result in leaving something on the table. By improving the analysis accuracy we will be able to provide flexibility but still adequately manage risk. By addressing cost, turn-around time, and risk, designers will still have the option to follow the optimum path knowing that DFM issues addressed.
Mike Gianfagna, Aprio Technologies -- For those that go the platform route, DFM will be the issue of the supplier and not the user. I believe there will always be a competitive need for silicon-level customization, however. Those users will worry about DFM.
Naeem Zafar, Pyxis Technology -- Not true! The leading-edge designers will always be working to optimize a design -- for space, timing, and now for yield and manufacturability, as well. It is a natural progression. The platforms you mentioned will have a place, but will never replace an SOC.
Nitin Deo, Ponte Solutions -- At 90 nanometers and below, DFM is all about design-specific issues. We have observed this in the past - when there are two different designs in the same technology, both fully DRC clean, the yield of those designs is completely different. Why does this happen? Because the way the process reacts to physical structures is highly structure dependent at these nodes. And that dependence is increasing. So, no matter what the underlying fabric is, as long as there are different designs, DFM issues will keep on increasing as the technology goes below 90 nanometers. Even companies like Xilinx are dealing with issues of catastrophic failure.
Riko Radojcic, Qualcomm -- Sooner or later, someone has to worry about polygons, and designers will have to worry about making sure that their designs are translated correctly into polygons. As DFM technology matures, many "DFM transformations" that we talk about today, will be absorbed into the physical design tools. But just like there is someone today worrying about simple design rules and DRCs, we will need to have someone tomorrow worrying about DFM models and simulators.
Rob Aitken, ARM -- Standard cell based design approaches will continue to have an area and speed advantage over reconfigurable and programmable platforms through at least 32 nanometers. DFx methods allow designers to improve upon this inherent advantage, through faster time to market, better performance/power/area, increased yield, or some combination.
Thomas Blaesi, SIGMA-C -- The lithography gap will continue to widen, moving down the process technology nodes and, therefore, DFM requirements will continue to be essential to make reconfigurable platforms work for future silicon technologies. There is also an increased demand for designers who understand DFM and can make designs work in the smaller process technologies.
Won-Young Jung, Nanno SOLUTIONS -- NO, DFM has to connect DFY. DFM/DFY is not new. They have existed since the semiconductor industry started.
Yervant Zorian, Virage Logic -- I think the answer here is yes. Not only because the designers will be working with reconfigurable platforms, but also because they will need to integrate these technologies with the rest of the chip. Without DFM tools, this will not be possible. Of course, they should never be buying IP without DFM.
9) I noticed at DesignCon, that the Business of DFM panel was almost more technical than the Technology of DFM panel. Is it an insurmountable problem to try to explain the context within which DFM tools are being developed and marketed? How many people really understand the problems being solved and the solutions being offered? How many VCs in the world really understand well enough to provide funding? (A complicated set of questions that have linked answers, I believe.)
Jacob Jacobsson, Blaze DFM -- We don't believe that a business discussion about DFM needs to be overly technical. The decision to adopt an electrical DFM solution that is architected according to the following three precepts becomes very compelling: 1) drive design (power and timing) requirements into manufacturing; 2) bring manufacturing awareness upstream into design; and 3) do not require major disruptive changes to the design flow, manufacturing handoff, or to the fab equipment line.
We have seen actual customer results where parametric yield was improved by double-digit percentages. On a high-volume design, this translates to tens of millions of dollars in cost savings and accelerates time to volume production by six months, all at a very low cost of adoption.
As far as VCs, the onus is on the DFM companies to explain their value propositions in a way that makes economic sense. It's difficult for DFM and DFY companies who are offering yield improvements of perhaps 1% -- 2%. At those levels, it's advantageous to get the VC bogged down in a technical discussion because the economic value just isn't there.
Atul Sharan, Clear Shape -- In the investment community, those who need to understand do. With regard to the designer community, as 65 nanometer is coming on line they are clearly seeing the issues and have made themselves heard - as was evidenced by TSMC's major announcement of a comprehensive DFM initiative that will release additional models and information to select DFM vendors in their qualification program. UMC and the IBM-Samsung-Chartered Common-Platforms also have similar DFM initiatives. Even a year ago some pundits were predicting that the major foundries would never release any of these additional models or information and they would be forced to become ASIC vendors - not only are they releasing it, they are leading the charge to accelerate adoption of true DFM on the design side.
Articles like these will go a long way in raising awareness -- DFM is indeed the case of "where there is smoke there is fire" and those who only see the smoke, and not the fire, will get burnt!
Dale Pollek, ChipMD -- Agreed, even some end-users who I've worked with -- people who had recent, failed first silicon to the point of writing off a lot of NRE, lost all customers and cancelled the design project -- even some of those are refusing to admit a new design tool could have averted the loss.
Unfortunately, some semiconductor companies are still too interested in cutting budgets and protecting one's job instead of acknowledging a new tool can enable them better success and profits in the future. There always has been a designer fear of “automation” tools replacing them, but this is the biggest fallacy that designers need to realize how to adjust and deal with the next design and improve competitiveness.
In part, I write this sort of attitude off to our currently overly conservative industry management who make only extra cautious moves and are worrying too much only about the daily stock P/E ratios than really looking ahead. Fortunately, there are many who are still smart enough to look ahead and understand that new small companies can provide a significant competitive edge. As I said from the start, it is nice to look ahead at 2006 as it does not look at all like any of the last four years!
David Thon, Cadence Design Systems -- There are many people who understand a broad spectrum of design technology, and many who understand a broad spectrum of manufacturing technology, but finding people who understand both and the interactions between them, to any significant depth is not common.
Dwayne Burek, Magma Design Automation -- One difficulty might be that the definition of DFM is not precise. Design for Manufacturing can cover anything associated with making a design that is manufacturable. So thinking of DFM as a stand-alone technology or business will lead to problems since DFM needs to be considered in the context of design and of manufacturing. But there are always opportunities to come up with better ways of doing things. And if you can show how this can lead to quantifiable yield improvement or accelerated yield ramp, then these are benefits that everyone is interested in.
Mike Gianfagna, Aprio Technologies -- Two answers. 1) Immature markets are hard to explain. With maturity comes clarity. 2) Many VCs have written checks for DFM funding. That fact proves beyond a shadow of a doubt that the VC community knows enough to make a choice … which VC is correct is another matter. Time is needed for that answer.
Naeem Zafar, Pyxis Technology -- You will be surprised how things have changed in the last 2 years. I just finished raising the money for our Series B funding, and DFM is understood today more than one may realize.
Nitin Deo, Ponte Solutions -- I agree with you. Right now the main issue is that when you say DFM, it covers so many aspects of the issue, that you have to go down to the technical detail to explain your point of view. But, that will go away over time. As designers start using these tools and start showing signs of real success, real difference in the predictability of yield and increased yields, with real trade-offs - not just black & white (pass or fail), the discussions will start moving toward benefits of using such tools.
It is much like selling life insurance. The first time someone sold it, he had to explain the details. But, once people saw that someone was actually paid from a life insurance, the discussion was all about 'what' can the agent do for them and not 'how'! Now, let me go and talk to 4 out of the 10 largest fabless companies 'what' Ponte is doing for them!
Rob Aitken, ARM -- The DFM environment continues to be very dynamic. The mutual influence of design and manufacturing has forced the abandonment of several positions that have been thought of as fundamental, including “design is finished at tapeout”, “yield is a manufacturing issue, not a design issue”, and “DRC clean guarantees yield”. This level of paradigm shift (apologies for using that term) always results in both under-appreciation of the magnitude of the changes as well as over-reaction to them.
Effective DFM does not require that every designer know how to configure the aperture and exposure of a stepper, but neither is it (yet) so simple that a magic set of tools will solve the problem without designer intervention. The level of awareness of the issues and nature of the solutions is increasing in both the business and technical communities, to the point where a strategy of predicting doom while waving around incomprehensible charts and formulae is unlikely to result in either VC funding or sales.
As people become accustomed to DFM, the technology part will disappear from the business panels. Other tools have passed through this transformation previously, a recent example being noise and IR drop tools. In some sense, this is a standard phase in any design automation process, but the VLSI design and manufacturing communities have been separated for so long that this transition is a bit more pronounced than most.
Thomas Blaesi, SIGMA-C -- Since DFM is the fastest growing part of the EDA market, it's being talked about by a lot of different people on a lot of different levels.
Regardless of how complex an issue DFM may be, a comprehensive DFM methodology can substantially improve the yield of a 65-nanometer fab, which translates into hundreds of millions of dollars in savings. That is attractive for designers, semiconductor manufacturers, and VCs.
Srinivas Raghvendra, Synopsys -- DFM is at the intersection of design and manufacturing, and a good understanding of DFM requires that we understand both design and manufacturing in some depth. This is a small group of people today, but that group is growing.
Won-Young Jung, Nanno SOLUTIONS -- Not many understand, because DFM is not only a design problem, but also a process problem. Very few VCs understand these issues.
Yervant Zorian, Virage Logic -- Designers should not need to know the details of what is inside the DFM tools that they are using. Like other trends in the past, the users don't need to know about the algorithms [at the heart of their tools]. And, as I said, if the IP has the necessary DFM, it can repair itself while being totally transparent to the designers, i.e. the users don't need to know the algorithms that solve problems [embedded there]. Some VCs though are more technical than others are, but in most cases VCs also don't need to understand the details to see the value.
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