So we made a critical architectural innovation: we reserved a separate FPGA for the interface logic and transactors, calling it the Reconfigurable Testbench (RTB). This provided two critical advantages. First, regardless of the DUT clock speed, we could run the RTB at a very high clock frequency to ensure that communication with the host happened as quickly as possible, without being burdened by the design logic. In fact, in ZeBu-Server - our latest and sixth generation of the emulator – multiple RTB FPGAs can drive the same DUT increasing dramatically the communication speed between the testbench and the DUT to an incredible transfer rate of five million transactions-per-second.
EDA WEEKLY: You said there were two advantages?
Yes. Second, any changes to the testbench could be compiled into the RTB without having to recompile the entire DUT. We completely decoupled the testbench from the DUT, and the impact has been profound enough to form a critical piece of the fundamental architecture that EVE uses.
EDA WEEKLY: So the choice of the Xilinx FPGA over a custom chip, and decoupling the testbench from the DUT were two EVE innovations that no other competitors had at the time?
If we look at the emulation market, standard FPGAs powered the early implementations of the machines but lost their attraction in the late 90s in favor of custom chips. After few mergers and acquisitions, only two players have been active in the marketplace in the past decade: Cadence and Mentor. Both use custom silicon, although in rather different architectures. Cadence’s emulators use chips with vast arrays of simple Boolean processors; Mentor’s chip implements a custom FPGA.
This makes EVE the only emulation provider to use an off-the-shelf device like the Xilinx FPGA.
The decoupling of the testbench from the DUT has been coded in the SCE-MI standard, but the uniqueness of EVE is in the implementation of the decoupling via our RTB approach.
EDA WEEKLY: You know, I kinda miss your “airplane analogy.” Let’s talk about the next phase of EVE’s flight, “takeoff.”
OK. Our takeoff phase began when we started selling a product. Our first model was simple by today’s standards: two FPGAs for the DUT on a PCI card. Users did the partitioning of their design across the FPGAs by hand and used native FPGA tools to generate the bitstreams. The machine was small, it was simple, we could develop it with modest resources, and it addressed a price-point that wasn’t being served by the big emulator providers of the day. We launched the ZeBu-ZV at DATE, 4-8 March 2002, Paris, and signed our first deal that year with TI’s wireless group. The ZeBu-ZV could handle designs up to 1.5 million gates, clocked up to 12 MHz. Our message was, that you could generate your chip masks with Zero Bugs (ZeBu) by verifying the design using EVE’s new emulator card.
We followed up the first product’s takeoff with a €3 million funding round in 2003, our first outside funding, to build some upward thrust, helping us promote the current product and feeding the development of follow-on product.
EDA WEEKLY: And then?
The ZeBu-ZV caught the eye of a large (un-named) company that was interested in bundling up a number of them into a box, treating the whole box as a single emulator. This may sound like an obvious thing to do, but scaling the hardware like this requires one critical additional step, and it’s a big step. It was no longer reasonable to expect users to partition their design across the many FPGAs inside such a system: you need to provide a compiler.
But this company said that they’d handle the compiler themselves; all it needed was the hardware. So we built the hardware for them – indeed, a brand new chassis with entirely re-designed boards that we called ZeBu-XL.
And the customer was delighted.
Of course, as you might expect, EVE had arranged with this customer in advance, that EVE could commercialize the box itself. Which meant that we had to create our own compiler.
EDA WEEKLY: So, suddenly, EVE found itself entering into the software business!
Well, we had already done a small amount of software development in ZeBu-ZV when we did a run-time environment that was unique in supporting transaction-based co-emulation via our RTB technology.
But you’re right, the really intensive software effort at EVE began with the development of the compiler, an ongoing effort that continues to this day: we currently have about 10 software engineers for each hardware engineer (a ratio not unlike that of the rest of the systems industry).
The ZeBu-XL took our capacity up to 50 million gates, although clock speeds eased to 5 MHz as a result of the multi-board clocking burden. Our own commercial version of the ZeBu-XL was launched in April of 2004.
EDA WEEKLY: So you had achieved take-off, but then what?
Oui, our take-off was successful, but, to maintain climb, we engaged in two further fund-raising rounds, in 2004 and 2006, bringing our total to €14 million. While the original ZeBu products were based on the Xilinx Virtex II family, we took advantage of Virtex 4 to do another generation of products, following the original serendipitous model of having a card version and a box version of the emulator. ZeBu-UF was released in mid-2006, bringing the PCI card emulator to 6 million gates at a top speed of 20 MHz on smaller designs; the boxed version, ZeBu-XXL, was released at the end of the year, with 100 million gates at a top speed of 10 MHz on smaller designs.
EDA WEEKLY: Sounds like EVE continued to gain altitude?
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-- Russ Henke, EDACafe.com Contributing Editor.
