Since Part 1 of this article was published on October 13th, events have begun to overwhelm. The dramatic speed with which the economic situation has further deteriorated in the past 5 weeks is shocking – globally, nationally, and within the tech sector. The global impact is evidenced by the G20 meeting that took place this past weekend in Washington, D.C. Whether the leaders of these countries are just putting on a show of solidarity or really intend to lay down ground rules for a unified response is unclear, but the intricate interconnectivity of the teetering global economy is obvious either way.

At the national level since October 13th, Congress has begun to express doubts as to the efficacy and transparency of the $700 billion financial sector bailout, and are resisting bailing out the withering American auto industry, the Dow has fallen an additional 6% (32% since 1 January), and the Nasdaq has lost an additional 18% (42% since 1 January). Meanwhile, October saw the sharpest drop on record in U.S. retail sales, while among other developments, Circuit City declared Chapter 11 bankruptcy, and announced it will lay off 20 percent of its workforce and shut 155 stores as increasingly frugal consumers have slowed consumption of high-tech gadgets and gizmos.

Meanwhile, those in the tech sector who thought they understood the dynamics of a downturn, having survived 2001, are now expressing concern that this time around, it may be deeper, scarier, and more impactful. Last Friday, Sun Microsystems reported an 18 percent workforce reduction, and unnerving tech news goes on from there.

Specific to EDA since Part 1 of this article was published, SNPS has lost an additional 12% (36% since 1 January); MENT has lost an additional 40% (49% since 1 January); LAVA has lost an additional 33% (82% since 1 January); and CDNS has lost an additional 24% (77% since 1 January).

In closely related news since October 13th, Mentor announced third quarter losses, and sharply reduced the company’s 2009 outlook. Cadence lost its CEO, all 4 Executive Vice Presidents, unexpectedly postponed its quarterly earnings statement citing potentially mis-allocated revenue from early 2008, announced layoffs of 625 employees plus unspecified numbers of contractors, and has been named in 11 class action lawsuits alleging inflated stock valuations based on inaccurate financials. At this writing, the company is under the direction of the Board, while names from the past and present are floated about in the industry as to who should lead the company going forward. Meanwhile, Magma stock has dropped sharply, as well, perhaps based on further fallout from a restructuring plan announced in early October and related layoffs.

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Take a chance on the future …

In this midst of this turmoil, ICCAD took place in Silicon Valley this past week. While there, I had a chance to speak with IBM’s Juan-Antonio Carballo, an expert on global tech investing. I asked him if EDA as an independent industry could survive, given the present circumstances in the semiconductor industry.

Carballo told me: “While the semiconductor industry is going through a tremendous transformation, with changes in the business model, nonetheless EDA is part of the economics of the industry and will survive –even if a number of players seem to be broken.

“EDA is a supplier to the semiconductor industry, where the reaction in EDA to [upheavals in] semiconductors is a second-order effect. Cyclic oscillations in the EDA industry are smaller than those in semiconductors, but if the semiconductor industry doesn’t return to double-digit growth again, it’s unlikely that EDA will either. So, it is difficult today to justify investing in EDA. Having said that, I see a tremendous amounts of innovation happening in EDA, although not as much as some might desire, of course.”

I asked Carballo, if double-digit growth is mandatory for success in EDA. He said, “It’s not mandatory, but that is the VC model. You have to see that kind of growth – whether in semiconductors or in EDA – if you want to attract venture capital. Yet, there is still room for growth around the edges of EDA, at the system level and software, and at the other end in tools for manufacturability.

“But, the real excitement today is in the areas of completely new materials, and design and technology related to clean technology. For example, solar materials, technologies, and systems – at some point there will be EDA tools to evaluate these systems, but again, it will be a while. Biotech will also need EDA at some point – new tools and software – but all of this is a ways off as yet, and will take a substantial number of years.

“My rule of thumb is an ‘investment constant,’ which is a multiple of the core industry to calculate the requisite growth of the smaller, supplier industry. For example, EDA is approximately a $5 billion industry today, while the semiconductor industry is approximately $250 billion to $300 billion. Divide those two numbers and apply them to solar technology, and you’ll see how large the solar industry has to grow before [solar] EDA can expect to attract [robust amounts of] venture capital.”

I asked Carballo if he had advice for the several hundred graduate students flowing around us in the hallway of the DoubleTree Hotel in San Jose between ICCAD sessions. He said, “They should be working on the tools and technology needed to address new problems. Grad students today need to be sure they’re not working on the problems of the past. If they’re working in the past, they’re not taking chances. More importantly, they need to learn to do research today, so they can do development later, and eventually succeed at sales!”

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Events of interest in the coming months …

* November 18th - IEEE SFBA Nanotech: Fueling Transportation (San Jose)

* November 19th - Panel Discussion: Making It through Tough Times (Santa Clara)

* November 19th - High-Level Design Validation & Test Workshop (Lake Tahoe)

* December 3rd & 4th - DDR3 DRAM Technology Training (Silicon Valley)

* December 3rd & 4th - IP08 Conference & Exhibition (Grenoble)

* December 9th to 11th - FPGA Summit (San Francisco)

* December 11th & 12th - edaForum08 (Dresden)

* December 15th to 17th - IEEE IEDM (San Francisco)

* January 19th to 22nd - ASP-DAC (Yokohama)

* February 8th to 12th - IEEE ISSCC (San Francisco)

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Best of Times …

Although I missed both the Synopsys Interoperability Forum and Mentor’s U2U event in November, I did have a chance to attend numerous other events over the last 5 weeks. There is a lot going on in and around our industry, downturn or no downturn!

* UC Santa Cruz on October 17 – The Baskin School Engineering at UCSC hosted a Research Review Day on campus in mid-October. The campus itself is a gem, set among the redwoods overlooking the Pacific, and the Engineering School is ramping up at a remarkable rate. Previously, students wanting to access an excellent engineering undergraduate program could start at UCSC, and transition to U.C. Berkeley as juniors to complete their degree. The caliber of the engineering program at Santa Cruz, however, has prompted that strategy of transition to Berkeley to cease.

Now well connected to Silicon Valley industry and investment partners, the UCSC faculty can brag on a wide range of research initiatives, including work in nonvolatile data storage, secure online collaborate content aggregation, nanopipettes and cell-sifter technologies for those inclined toward the biological, and exploration of various human/computer interface problems. The entire program at UCSC is impressive – and growing. With over 700 students, and a fully functional remote campus at NASA Ames in Mountain View, look for lots of innovation and leadership to come from the Baskin School of Engineering at Santa Cruz going forward.

By the way, the morning keynote was delivered by Prith Banerjee, Senior VP and Director of the worldwide HP Labs. He gave a rousing speech connecting the spirit of the mid-20^th century Bell Labs with the scope of interests and investments driving today’s HP Labs. Unfortunately for Dr. Banerjee, none of the 2008 inaugural research awards – upwards of $3 million handed out by HP to a gaggle of global institutions in industry and academia to help drive innovation in 23 (!!) different areas of technology – managed to land in the hands of any of the researchers at UCSC, many of whom were in the audience for Dr. Banerjee’s address. I suspect before he comes back next year for UCSC’s 2009 Research Review Day, Banerjee will be sure his awards committee looks more carefully at the quality of the work being done at UCSC, and the proximity of the campus to the HP Mother Ship.

* Test Week and ITC from October 26th to 31st – Test is a special neighborhood in EDA. For many years, it was a cul-de-sac where mainline players in EDA rarely stopped off. These days, however, all of that has changed. Now, thanks to the great difficulties in getting things manufactured accurately, and accomplishing big yield despite small geometries, it turns out a lot of the solutions to design-for-manufacturability rest in the cul-de-sac of design-for-test.

Hence, despite the downturn and gloomy predictions of yet another Armageddon in the tech sector, and Silicon Valley in particular, this year’s International Test Conference seemed to me to be very well attended. The exhibit hall was lively and the opening keynote on Tuesday, October 27th, had many hundreds of people in attendance at the Santa Clara Convention Center; Cisco VP Mike Lydon’s talk offered a comprehensive review of the relationship of test to successful silicon.

Afterwards, I had a chance to speak with ITC Program Committee member, Freescale’s Carol Pyron, as folks were milling about in the ballroom after the close of the plenary session . She emphasized that “test is not a cul-de-sac anymore! Test touches all parts of the process, and it always has. People just recognize it these days more than ever before.”

Pyron added that despite the current economy, “Companies absolutely have to invest in a down market if they hope to be ready for the next uptick. You have to tighten the bolts, and push the technology because the uptick always arrives!”

I also saw Tets Maniwa, long-time EDA observer, at ITC. With regards to the Cisco keynote, he said: “It’s interesting to see they’re mentioning power more and more here at ITC. Way back in the dark ages, I wrote an editorial suggesting that the problems in test would escalate as problems in power increased. Now I see that situation is being fully recognized here at ITC. There are some solutions being looked at right now, but none really exist as yet. That’s certainly a market opportunity that continues to exist for those who can take advantage of it.”

[Editor’s note: Tets Maniwa provides coverage of the Cisco keynote , and the October 29th ITC invited talk given by U.C. Berkeley’s Jan Rabaey in EDA Confidential ]

* Phil Kaufman Award Dinner on October 29 – Sponsored by EDAC, CEDA, and White & Lee LLP, and managed by Marketing on Demand, the annual Kaufman Award Dinner was as civilized and sophisticated as one would expect for a dinner honoring Synopsys CEO Aart de Geus. The several hundred people in attendance were welcomed by EDAC Chair Wally Rhines of Mentor Graphics fame, and CEDA Chair John Darringer of IBM fame. Both men warmly congratulated de Geus for his decades of accomplishment, while U.C. Berkeley’s Kurt Keutzer gave the main address, outlining in detail the story behind the technology and the people that have put Synopsys and Aart de Geus on the map.

A video testimonial to de Geus’ contributions followed Keutzer’s comments, and included congratulations from U.C. Berkeley’s Alberto Sangiovanni-Vincentelli, Synopsys Fellow Brent Gregory, Synopsys Board Member Bruce Chizen, Silicon Valley Leadership Group CEO Carl Guardino, Synopsys President Chi-Foon Chan, Applied Materials Board Chair Jim Morgan, Synopsys Senior VP Deirdre Hanford, Synopsys VP Rich Goldman, The Center for Corporate Innovation’s Sanjay Vaswani, and former San Jose Mayor Susan Hammer. Credited for his commitment to local education. through the Synopsys-sponsored Silicon Valley Science & Technology Championship, and local culture through his leadership of the San Jose Jazz Festival, Aart de Geus was described repeatedly throughout the evening as a Renaissance Man.

When Dr. de Geus finally took the podium to express his appreciation for the evening’s commendations, he started by thanking his family with great emotion – they were seated prominently at the head table – and all those who have contributed to his career. He made special mention of his long friendship with Chi-Foon Chan. Per de Geus, Chi-Foon and Aart are twin brothers, separated at birth, and coincidentally brought back together to successfully share in leading Synopsys to its current ranking in the EDA market.

Just in case anyone doubted that ranking in the market, Dr. Keutzer began his remarks with a simple bar chart. As of October 29th, the day of the Kaufman dinner, the market capitalization for Synopsys was greater than that of Cadence, Mentor Graphics, and Magma combined. For some reason, that particular bit of market data seemed wildly amusing to Keutzer‘s audience.

By the way, the evening also included a Film Noir moment, ala Citizen Kane, that included cameo appearances from Wally Rhines, Ed Chang, Ed Sperling, and John Blyler. Seeing Rhines channeling Warren Muffet (sic) remembering Phil Kaufman was worth the price of admission, as were the reminiscences of Ed Cheng enjoying his golden years by reflecting on VLSI technology, synthesis, and layout. I’m pretty sure Orson Wells would have loved it.

* ICCAD from November 9th to 13th – A longtime lynchpin of the autumn tech conference cycle in Silicon Valley, the IEEE International Conference on Computer Aided Design was again the destination for the EDA industry this past week in San Jose. As mentioned above, there were hundreds in the DoubleTree Hotel attending sessions, panels, keynotes, and observing/participating in the annual CADathlon grad student design competition.

I attended 5 events at ICCAD: Monday’s panel discussion moderated by Cadence’s Andreas Kuehlmann, Monday’s SIGDA dinner honoring Achievement Award winner Ed McCluskcy from Stanford, a Tuesday morning tutorial on Graphene Nanoribbon FETs given Rice University’s Kartik Mohanram, a lunchtime keynote given by EPFL’s Giovanni De Micheli, and a Wednesday afternoon Birds of a Feather session featuring a host of EDA bloggers discussing present opportunities and future growth for this increasingly pivotal conduit of communication.

* The Kuehlmann Panel included ARM’s Rob Aitken, Intel’s Jerry Bautista, Carnegie Mellon’s Wojceich Maly, and U.C. Berkeley’s Jan Rabaey. The conversation centered around extending Moore’s Law into the foreseeable future, a somewhat tried-and-true topic that took on amazingly contentious dimensions in the hands of the four panelists on November 10th. For starters, Kuehlmann compared the history of aeronautics with that of the semiconductor industry, and concluded that the most advanced aero-tech has rarely been embraced by the commercial aviation industry, because few companies can afford the implementation of leading-edge innovations.

ARM’s Aitken took it from there and explained in detail why Moore would continue on – multiple VT, strained silicon, hi-K materials, immersion lithography, and a mixed bag of tricks from EDA. Not surprisingly, Intel’s Bautista said the answers to life’s questions resides in everything multi-core/multi-thread. Look at Intel’s 80-core products, he admonished, built on standard 65-nanometer processes. CMU’s Maly went next and went off like a rocket. Difficult to tell sitting in the audience if his agitation was authentic, but the gist of his message was it’s 3D or No Go; Maly’s message mixed with lots of aspersions cast on the larger semiconductor industry for continuing to fail to listen to his prophetic voice. UCB’s Rabaey wrapped up the opening statements by revisiting the topic of his ITC keynote on interconnected mega-memory computational cloud structures.

Once the opening salvos had been delivered by the Gang of Four, the discussion went forth in a distinctly animated way. Not sure I was tracking everybody’s particular territory or point of view, but in the end Kuehlmann could feel satisfaction that he’d created far Moore than a molehill out of a mountain – there are some thorny issues here, that simply will not go away anytime soon. Meanwhile, it would have been really interesting to sit with Kuehlmann, Aitken, Bautista, Maly and Rabaey, after de Micheli’s keynote talk the following day. All told, the differences between theory and reality – at both the Monday panel and Tuesday lunchtime address -- seemed closer to a chasm than a coming-together at ICCAD.

* The ACM/SIGDA dinner at ICCAD on Monday evening showcased the 2008 SIGDA Pioneering Achievement Award Winner, Stanford’s Ed McCluskey. Professor McCluskey gave a deceptively unstructured, organic talk, mixing personal recollections of his long career with highlights of seminal papers and books – several of which he authored or co-authored – that have influenced design and test over the last 70 years. The audience was hard pressed to keep up with McCluskey as he peppered them with questions, Socratic style, to test them on their knowledge and understanding of the importance of each work he mentioned.

From my vantage point at the back, most of the stellar technologists in the room barely earned passing marks on Dr. McCluskey’s impromptu orals, but they swallowed their pride and made their way to the podium one by one, nonetheless, to warmly celebrate McCluskey’s accomplishments and mentoring. The congratulatory queue included Virage Logic’s Yervant Zorian, U.C. Berkeley’s Bob Brayton, Synopsys’ Tom Williams, TIMA Lab’s Bernard Courtois, EPFL’s Giovanni De Micheli, DAFCA’s Miron Abramovici, University of Illinois’ Ravi Iyer, and Carnegie Mellon’s Daniel Siewiorek.

[If you were not at the dinner, try answering these questions: 1) Why was Shannon’s 1938 paper so important? 2) When and who wrote the paper first describing stuck-at faults? Don’t know the answers? Dr. McCluskey’s talk was taped; do your homework before you tune in.]

* The Graphene Nanoribbon FET talk was part of a morning tutorial detailing design and CAD challenges in graphene electronics. Pretty esoteric stuff, but if Juan-Antonio Carballo is right, it’s the stuff of the future – novel materials and applications that can help stretch the boundaries of EDA. Kartik Mohanram detailed some of the edge-quality issues that cause non-idealities to occur in these two-dimensional graphene lattice structures during his talk. Interesting that these materials can have metallic or semi-conducting qualities, depending, so intuitively there seems to be a lot of promise here.

By the way, Stanford’s Subhasish Mitra, session moderator, kept Mohanram on his toes, but not off balance, throughout the presentation with repeated questions. If GNRFETs ever get off of the drawing board into production, rest assured the technology will have been thoroughly vetted first by the ICCAD community & friends.

Dr. de Micheli’s Tuesday keynote was a rip-roaring romp through everything that EDA could be, if EDA wanted to be – CAD tools for more efficient energy sources and CAD tools for a host of biological design challenges. Building on work from various universities around the world, and illustrated with images from a host of papers and R&D labs, de Micheli explored the idea of a SPICE-like tool for biochemical abstractions, simulations, and testing. He talked about the difference between engineered systems and biological/organic systems – the former being difficult to design and manufacture, while the latter tend to be efficient, ultra low-power, low voltage, and amazingly robust.

Like the McCluskey talk, Professor de Micheli’s talk was taped, and worth committing an hour to review if you were not there. I am 100-percent certain that within 10-15 years, everything de Micheli discussed will have moved from the paradigm of a lunchtime keynote into the more scientific, and technically acute paradigm of the regular sessions at ICCAD. Mark my words.

* The EDA Bloggers “Birds-of-a-Feather” meeting was a lively gathering, to say the least, on November 12th at ICCAD. If you want to hear more of my impressions of the meeting, I invite you to go to my ‘blog’ at EDA Confidential. If you don’t think my site qualifies as a blog, welcome to the wacky world of blogging, where semantics are still as hot a topic as the logistics behind the medium. [ Where the Boundries of Blogging Blur ]

* Finally, it wouldn’t be ICCAD without the CADathlon, a marvelous, annual design contest that pits 40 EECS grad students from 20 universities in a marathon battle of intellect and design savvy. This year’s winner was the team from Universitat Politècnica de Catalunya in Barcelona. Excuse my excessive optimism, but in observing many of the grad students in attendance at ICCAD, the future of this industry surely resides in bright and energetic minds – no matter what the graybeards and naysayers may say. There is a great future ahead. Again in 2008, ICCAD showcased new and novel technologies, and future opportunities for innovation and success. It was exhilarating to be there just to listen in.

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Industry on the march …

Do not tell me this industry is dead in the water, or withering in the face of a global downturn. People are working hard, hoping to stay employed, and bringing energy, intelligent and indefatigable optimism to their work. I’m aware that many have been laid off, but all of us have been through that. We have to believe there is a future here, given the depth and breadth of the following news out of a variety of companies:

* CEDA and ACM SIGDA together announced a call for nominations for the A. Richard Newton Technical Impact Award in Electronic Design Automation. Per the Press Release: “The yearly award for outstanding technical contributions honors the late Dr. Richard Newton, a luminary in design automation academia and industry, and dean of engineering at U.C. Berkeley, who died in 2007. The award will be presented to an individual or individuals for outstanding technical contributions to EDA, recognized over a significant period of time. Qualifications will be based on a high-impact, seminal paper published by either ACM or IEEE nominees at least 10 years ago. Nominations are being accepted until May 15, 2009.”

* Accellera announced voting has confirmed solid, ongoing leadership for this pivotal language standards body: Sun’s Shrenik Mehta as Chair; Mentor Graphics’ Dennis Brophy as Vice-Chair; Synopsys’ Karen Bartleson as Secretary; and Magma’s Yatin Trivedi as treasurer.

* Apache Design Solutions announced it has been named in the top 15 of Deloitte's Technology Fast 50 Program, described as “a ranking of the fastest-growing software and IT companies in the Silicon Valley.”

* ARC International announced that “one of the top 10 SoC design companies in Taiwan” has taken an ARC license. Per the Press Release: “The new customer is incorporating ARC’s low power solution into cellular baseband designs targeting the worldwide cellular handset market. The company chose ARC IP because it could custom tailor the performance, while achieving the small size and battery efficiency demanded of chips servicing the growing global handset market.”

* ARM announced IP library support for IBM’s newly announced 45-nanometer SOI foundry offering. I spoke with Tom Lantzsch, Senior VP for the ARM Physical IP Division, on November 14th about the ARM announcement. Lantzch said ARM sees six focus areas wherein the SOI news is critical:

1) A market-timing point of view where today’s consumer content is focused on supporting content for the home and/or back office; 2) SOI can now be used at different performance levels and now addresses previous price/performance versus bulk production concerns; 3) SOI no longer lags bulk technology process nodes; 4) Having open foundry availability to 45-nanometer SOI will stimulate product growth in many sectors; 5) ARM’s library offerings that support IBM’s announcement means reduced barriers for those in the design community who want to work in this technology; and 6) There are now 20+ members in the ARM-sponsored SOI Consortium, spanning everyone from end-users to substrate providers. If there are unique tools needed for SOI design, they will be emerging from efforts out of that consortium.

* ASSET announced it has joined Synopsys' in-Sync program for third-party suppliers of EDA-related products. ASSET VP Alan Sguigna is quoted: "As the need for embedded instrumentation becomes more acute in the industry, it is incumbent upon us to support and interoperate with those tools that chip designers are using to insert this instrumentation. Then chip and circuit board designers, manufacturing engineers and even field service personnel will be able to use ScanWorks to access, automate and analyze embedded instrumentation throughout a system's entire lifecycle."

* Berkeley Design Automation announced what it calls “the industry's first closed-loop noise analysis of fractional-N PLLs at the transistor level. Combining transient noise and periodic noise analysis in the company's Noise Analysis Option device noise analyzer, designers can now optimize and characterize all fractional-N and integer-N PLLs for phase noise and jitter prior to silicon fabrication. The result is improved performance, lower power, and faster time-to-market.”

* Cadence announced an expansion of its the ActiveParts Portal will now offer PCB design teams “greater access to key component information.” The company says it is working with Supply Frame, Inc. “to provide engineers with new choices and even greater access to the component information they need to create their designs.

In addition, Cadence announced new enhancements for the company’s OrCAD Capture CIS and Allegro Design Entry CIS products. Per the Press Release: “Technology and enhancements introduced for the OrCAD Capture CIS and Allegro Design Entry CIS products include a new capability called Context-aware Non-Linear Graphic Editing. The capability is a new schematic editing technology for dense designs that provides a magnifying auto-zoom between focus points during editing operations.”

* Calypto Design Systems announced a new version of its SLEC verification tool; supports fixed-point datatypes and system-level memory interfaces commonly used in wireless, video and image processing SoC devices. Calypto CEO Tom Sandoval is quoted: “Calypto has added new capabilities to comprehensively verify the latest high-level synthesis features.”

Calypto also recently announced Pixim used Calypto’s PowerProCG to significantly reduce power consumption in a new Pixim video imaging processor. Calypto also announced a collaboration with Forte on a SystemC verification and implementation design flow for consumer and multimedia products.

* Carbon Design Systems announced volume shipments of it SoC Designer. Recall that: “Carbon assumed development, support and sales of SoC Designer from ARM in July 2008, and now offers a complete system validation solution with cycle-accurate system modeling, cycle-optimized platform creation, execution and analysis, and cycle-accurate model kits for ARM IP.”

* CAST announced that 40 CASTcores have undergone evaluation and testing using Mentor Graphics Precision Synthesis FPGA tool. Daniel Platzker, Mentor Graphics FPGA synthesis product line director, is quoted: “After working with CAST on these cores, we’re happy to recommend them to our mutual customers for use with Precision Synthesis as part of our comprehensive, vendor-independent FPGA design flow.”

* Ciranova has chosen the excellent Eric Filseth to lead the company as CEO. Given that EDA legends Jim Solomon, Jim Hogan, and Ed Petrus are all on the Board of Directors (Petrus is also Ciranova COO), you will definitely be hearing big things from this company going forward. Stay tuned!

* congatec AG announced its conga-QA computer module based on the Qseven form factor (standardized form factor of 70mm x 70mm). It’s “fitted with the latest Intel Atom Z5xx range of processors and US15W system controller hub. Note this from the congatec: “The Qseven platform was specially developed with an eye on the latest low power processor technology and demand for small physical size.”

* Denali announced its PureSpec verification IP that the company says allows “device and system designers to begin advanced SuperSpeed USB development.” Jeff Ravencraft, USB-IF president and chairman, is quoted in the press release: "We are pleased to see this announcement from Denali, supporting the USB 3.0 specification, as it will help developers bring SuperSpeed USB products to market quickly and support compliance to the USB 3.0 specification with their USB VIP solutions."

* eASIC announced a series of video IP cores to the company’s Nextreme ASICs. Per the Press Release: “The combination of eASIC’s technology and Video-Cores’ Core Values video IP provides video system designers with a quick path to implementing custom functions such as video scalers, color-space converters and ITU 656 interfaces.”

* Envis announced AJ Sen has been named CEO of the company, Holly Stump is now the VP of marketing, and two distinguished technologists – U.C. Berkeley’s Bob Brayton and USC’s Massoud Pedram – now constitute the Technical Advisory Board for the company. Look for significant developments out of Envis going forward.

* eSilicon announced it delivered working silicon on the world’s FPGA for Achronix Semiconductor Corp. Jack Harding, chairman, president and CEO of eSilicon is quoted: “The Achronix application required an advanced process node, very complex internal circuitry, and several high-speed multi-protocol interfaces. eSilicon successfully delivered working first-pass silicon to Achronix, enabling it to deliver product to customers quickly.” Also in the Press Release: “eSilicon also managed design complexities to deliver a sophisticated package for the device. With multiple 10 Gbps interfaces, as well as a four 72-bit wide DDR2/3 memory interface operating at 1066 GHz, maintaining signal integrity was a critical element of delivering a working design.”

* EVE and Concept Engineering announced a worldwide partnership agreement, whereby “Concept Engineering will offer a free, time-limited usage license of its graphical viewing software to design teams employing EVE’s popular emulation platforms. The agreement includes plans for EVE and Concept Engineering to further integrate their tools.”

* Gemini Design Technology announced what the company is called “the industry’s fastest SPICE-accurate simulation technology specifically developed to leverage the throughput advantages of multi-core computing. The company’s native multi-threaded technology has demonstrated run times and capacity of up to 30x that of earlier generation analog simulators, and up to 10x improvements over first-generation multi-threaded approaches. The technology has been under development for three years and is being used in several production design environments, as well as benchmarked extensively against state of the art analog simulators, including multi-threaded ones.”

EDA industry guru Jim Solomon is Executive Chair of the Gemini Board of Directors. I spoke with Jim by phone and he told me, “I’m spending a lot of time on the company right now. I hired Kent Jaeger [VP of Marketing & Sales], I go on sales calls, and sit in on strategy meetings every week.

“The company started in 2005, and has had the 3 years needed to develop new products and roll out for the market. Our product focus is 100-percent SPICE-accurate simulation, [with a] market focus on mixed-signal applications, and the cell characterization space. We bring a lot of value when we focus on the mid-to-high complexity stuff, and also the high-end SoC market, as well. We also know we can reduce [simulation times] from days to hours, and from hours to minutes.

Kent Jaeger was also on our call. He said, “We were at a big IDM last week, and Jim asked them what their Number 1 headache is these days. The CAD manager said it’s speeding up SPICE – that’s his Number 1 Care-about, to improve SPICE-accurate simulation.

Solomon added, “Some companies are running simulations for weeks to get one compete simulation. They’re having to chop up the design into smaller blocks, and then drive them like made. Intel and IBM, for instance, have tens of thousands of SPICE simulations running; it’s surprisingly intensive.

“Also, we’ve tried to optimize for ultimate multi-core performance, for better implementation. We’ve threaded more aspects of a SPICE-accurate simulator than any other company in the industry, Some of our competitors have announce they’re planning to go after that [ability], but we’ve already got it today. For the last 20 years, people have said it wasn’t possible to thread the core algorithm in SPICE, but somehow it has all came together for us.

Baolin Yang is the Founder & President of Gemini. I asked Solomon if there would be any potential problems, given that Yang had senior engineering positions at Cadence. Solomon said, “There are no problems. Baolin went out [of Cadence] with empty hands. And, Cadence has been quite aware all along of what we are doing; we check in with them regularly.”

* GSA (The Global Semiconductor Alliance) and NMI (the National Microelectronics Institute) announced a “collaborative memorandum of understanding to form an organizational alliance.” Let‘s see: I think this means there’s gonna be a lotta talking between these two group, and that’s undoubtedly a good thing. Semiconductor folks should definitely be talking with the Microelectronics folks.

* HiFN announced a proposal for a secure hash algorithm standard has been submitted to a competition sponsored by the National Institute of Standards and Technology. The development team included Hifn Chief Scientist Doug Whiting, Bruce Schneier, and cryptographers from Microsoft, Intel, U.C. San Diego, the University of Washington, PGP, and Bauhaus-University Weimar.

* IAR Systems announced the launch of IAR Embedded Workbench for Atmel AVR32 Version 3.10. Per the Press Release: “IAR Embedded Workbench for Atmel AVR32 is an IDE with project management tools and editor combined with a highly optimizing AVR32 compiler supporting C and C++, and featuring configuration files for all AVR32 devices.”

* IMEC and Panasonic Corp. announced an agreement whereby they’ll be working jointly in the “semiconductor, networks, wireless, and biomedical fields.” They say work will happen at IMEC facilities in Belgium and the Netherlands. There has already been successes from IMEC and Panasonic working together: “The world's first mass production of the SOC with 65-nanometer and 45-nanometer processes such as Panasonic's UniPhier uses the results of the joint research with IMEC.” Look for more results in the coming years.

* JEDA Technologies announced the premier release of the JEDA Validation Tools Suite, “an integrated ESL model validation solution that establishes a predictable and efficient validation flow for high level models. The Suite consists of advanced code coverage for SystemC models, functional data coverage, temporal rule checks native in SystemC, intelligent traffic generators, and a test ranking system that prioritizes regression tests based on various user decision criteria.”

JEDA CEO Eugene Zhang and I spoke recently about this new release, and the need for the industry to fully embrace TLM 2.0. In particular, Zhang spoke about the idea that ESL 2.0 = EDA 4.0, as suggested in my October 2006 EDA Weekly article.

Per Zhang: “I think today we are still in ESL1.0, still in the process of turning a few characteristics laid out in your article into a reality. This will take some time, because ESL has lost some momentum and only had limited success so far.

“Speaking from personal experience, from 2005 to 2008, while JEDA was working in the field of ESL, I observed numerous false starts and backfires experience by early adopters of ESL – particularly among the leading semiconductor companies in Japan. There were multiple reasons, but one of the key reasons was a failure on the part of the technology to meet expectations. Bad quality in ESL products caused tremendous pain for the customers, things like problems between the IP models and the virtual platforms coming from different sources were nightmares for the customers. The reaction from users has been to politely keep ESL usage inside the CAD groups in Japan, restricted to in-house solutions in Europe, or an ongoing wait-and-see attitude in the U.S.

“Now with the release of TLM2.0, however, we see there is a second chance for ESL, but it absolutely must start with a bang. It simply can’t stop with flashy demos, and then fall apart as the customers start to us it. It must be delivered able to meet real production requirements.

“What I was at Juniper, the first question asked of us was always – ‘How did you verify your Verilog IP model?’ – whenever an IP provider knocked on the door. If that question was not adequately addressed, the rest of the conversation was moot. Similarly for ESL, if IP providers are not ready to answer the verification question, or even if the ESL end-users don’t ask the question, if means the whole transition is not a serious one, and ESL will continue to go nowhere.

“ A successful ESL solution provider absolutely must have multiple-domain expertise, which is actually quite difficult to assemble – which is yet another reason for the slow adoption of ESL. Worse yet, if self-awareness of ESL issues is not there among the players, the move will not happen. We need dynamic leadership to make ESL happen sooner rather than later, but it will eventually happen.”

* Magma announced that the company’s Titan Analog Migration will be incorporated into TSMC’s analog design environment. Per the Press Release: “TSMC uses Titan AM to port its analog IP building blocks to new process nodes so its customers and partners can quickly implement their designs in TSMC's advanced technologies.”

* The MathWorks announced the Simscape language, described as a “new capability that enables textual authoring of physical modeling components, domains, and libraries in the Simulink environment. The new language is included in Simscape, which extends Simulink for modeling and simulating mechatronic and other multidomain physical systems using a physical network, or acausal modeling, approach. [It] enables engineers to develop reusable models of components and systems for rapidly advancing technologies, such as fuel cells, wind power systems, and hybrid electric vehicles.”

By the way, the folks at The MathWorks assure me that you needn’t despair because you’ve got yet another language to learn to do your job. They say this new language is fully adapted to the widely understood MATLAB. Therefore, worry not.

* Mentor Graphics announced the Mentor Graphics PCB Design Laboratory at the Lake Washington Technical College in Kirkland, Washington. The company says, “The primary purpose of the lab will be to teach PCB design methodologies based on the Mentor Expedition tool flow. Under the auspices of Mentor’s Higher Education Program, Mentor has donated more than $8M worth of EDA software and support to enable students of LWTC to graduate with in-depth knowledge of the latest PCB design methodologies. In addition, Mentor has donated computing hardware with which to conduct the classes.” Nice!

* MIPS Technologies announced the MIPS Navigator ICS, which the company says will allow embedded de3velopers to code, debug, and analyze Linux systems on MIPS-based SoCs and embedded systems. Per the Press Release: “Navigator ICS brings together the industry's leading tools and technologies for MIPS development in a cohesive, off-the-shelf product, with new and innovative components for Linux development.”

Allen Watson, MIPS product marketing manager, told me on a recent phone call: “We’ve got extra modules in this suite to help debug Linux systems, and generalize them to make them better for the 60-to-70 percent of our customers who use Linux.”

I asked Watson to describe those customers: “MIPS licenses cores to semiconductor vendors, either large companies like Broadcom or smaller fabless companies. Broadcom, for instance, may come out with a chip and need some tools to get it running, Then they sell that chip to tens of other small or large companies, so now we have two sets of customers – our customers, and our customers’ customers. Sometimes the needs of the two groups are slightly different, so we need to understand both of them and which tools are suitable for use in each setting.”

Watson explained why it‘s easier for MIPS to provide these tools, rather than have the customers develop them in-house. “We are integrating a lot of things together with Navigator ICS. It’s really offers better time-to-market, plus a reduced risk and cost to our customers, as well. If the customers try to do this on their own, they have to spend the time and bear the risk. At some point our customers reach a point where they realize the advantages of having us do this integration for them.”

Why don’t EDA vendors provide these tools? Per Watson: “There are many tools available for our third-party ecosystem partners, but we’ve done some things with our tools which reach deep in to our cores – things that a third-party vendors would not find it worthwhile to do.”

Jack Browne, MIPS VP of Marketing, was also on the call. Browne said, “At the end of the day, it’s about helping customers get to production, to enable them with as much performance as possible. By letting our customers tune the Linux kernel on their hardware, by enhancing their capability in using open source, we’re helping them exceed expectations with their customers. They already know that MIPS-based systems are really good out in the marketplace. Now with this suite, we’re providing additional design debug capabilities that allows customers to produce more efficient hardware and software.”

* Sigrity announced SpeedXP 8.1 beta, as well as enhancements to the company’s SPEED2000, PowerSI, PowerDC, Broadband SPICE, XtractIM, OptimizePI and UPD products. Folks are definitely working hard at Sigrity. Downturn? What downturn?

* Synopsys announced a “complete, single vendor SuperSpeed USB IP solution consisting of the DesignWare device controller, PHY and verification IP … includes a SuperSpeed USB virtual platform and drivers to aid software development. Utilizing elements from a single vendor enables designers to quickly create SuperSpeed USB-based designs from concept through implementation and software development.”

* Tensilica announced it has ported the RealVideo codec from digital entertainment services company RealNetworks, Inc. to the 388VDO Video Engine. Per the Press Release: “The RealVideo codec expands the applicability of Tensilica's 388VDO video processor to products that efficiently display Internet content on everything from mobile devices to extended standard definition DTV.”

* TSMC announced volume production of its 40-nanometer semiconductor manufacturing process with the ramp of its 40-nanometer General Purpose (G) and Low Power (LP) versions, first announced in March 2008. Per the Press Release: “A comprehensive design infrastructure including library, IP, design flow, engineering service, and monthly CyberShuttle prototyping vehicles is also ready for these two processes.”

In conjunction with the announcement, I had a chance to speak by phone with Di Ma, TSMC Vice President for Field Technical Support. Ma told me, “Because the technology comes in two versions, general purpose and low power, we can cover a wide range of markets. We have quite a few early adopters for this new node, including Altera, AMD, Broadcom, PSI, Marvell, Nvidia, NXP, ST, and Sun – all working at various stages of adoption.

I asked Ma to compare the adoption of 65-nanometer technology to 45. He said, “The adoption rate at 40 is as good, if not better, than that at 65. [Of course], we are grateful for the collaboration of our customers, as we have migrated from 90, to 80, to 65, 55 and now 40 nanometers. Foundry customers have great design capabilities, and they help push us as they take advantage of our newest technology offerings. We see the design-enablement part of our role in the ecosystem as [more than just] our technology per se – it’s a total solution, where our approach is one of true collaboration.”

* ViASIC announced that Achronix Semiconductor Corp. used ViASIC’s ViaPath place and route software in Achronix CAD environment (ACE). ViASIC says, “ViaPath is the only commercially available tool that can perform optimization, placement and routing for standard metal (one-mask or two-mask) programmable designs. The principles used in ViaPath are equally effective for structured ASICs and synchronous or asynchronous RAM-based FPGAs.”

* Xilinx announced the Xilinx Automotive Optical Flow FPGA implementation for vision-based driver assistance systems. The company says the new release “integrates high-performance image processing capabilities from Digital Design Corp. (DDC) into a cost-effective, programmable platform that can be customized to support a variety of advanced applications, including pedestrian detection, collision warning, sign recognition, blind spot detection, back-up and parking aid.”

* ZMD AG announced a new device that’s a “multifunction temperature logger and smart” RFID that allows users to “precisely monitor and record temperature and humidity throughout the shipping process … and avoid the necessity of discarding products that may only have been briefly exposed to temperatures outside the permitted range.” Very cool, but then that’s exactly the point, isn’t it.

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Worst of Times …

For the EDA industry, the ongoing Cadence saga has been disturbing, to say the least. In the following articles, basically two different options are laid out. Take all of the bad news of late, internalize it, solve the pressing need for leadership and vision, and move forward, or continue to 'function' without leadership because the best option is to prepare to be sold to the most appropriate bidder.

My article, Weary Wednesdays at Cadence , looks at the public face of the company over the last few weeks, including a list of possible candidates for CEO gleaned from suggestions that have come my way.

Cadence: What’s going on behind the scenes is a contributed article, with a far different tone and conclusion. If the author of this article is correct, the Board of Directors at Cadence is not looking for a new CEO at all.

You can find the full EDACafe.com event calendar here.

To read more news, click here.


-- Peggy Aycinena, EDACafe.com Contributing Editor.