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SATA 6G PHY in TSMC (40nm, 28nm, 16nm)
dwc_sata6gphy_tsmc
Features
SATA 6G PHY in UMC (40nm, 28nm)
dwc_sata6gphy_umc
Features
SATA I/II SerDes
Features
SATA Verification IP
Features
SATA-II PHY IP Core
Features
SATA-Xactor
Features
SATA2-Port_PCI_Host_Controller
Features
SCADC12F.C35
Features
Scan Ring Linker
Scatter-Gather Direct Memory Access (DMA) Controller
Features
SCR -- Smart Card Reader Controller Core
Features
SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller IP
Features
SD 3.0 Device Controller
Features
SD UHS-II PHY IP (ZRSLSIPSDUHS2PHY)
Features
SD UHSII PHY supportings SD4.x
SD Video Codec Integrated Solution
v-MP2010MOB
Features
SD-ADC-CA
Features
SD-ADC-CEC
Features
SD-ADC-PDC
Features
SD-DAC-CEC
Features
SD-DAC-PDC
Features
SD/eMMC in TSMC (28nm, 16nm, 12nm, 7nm)
dwc_sd_emmc_tsmc
Features
SD/SDIO 3.0 Device COMBO Controller
Features
SD/SDIO Device IP Core
Features
SD3.0 / SDIO3.0 / eMMC4.51 Host Controller IP
Features
SD4 / eMMC 5.0 Hardware Validation Platform
Features
SD4.0 / SDIO4.0 / eMMC4.51 Host Controller IP
Features
SDIO 3.0 VIP
Features
SDIO UHS II VIP
Features
SDLC: Controller Core
Features
SDM for Radio Frequency Applications (RF)
Features
SDRAM
Features
SDRAM Controller
SDRAM multi-client core
Features
SECURE CLOCK GENERATOR IP
Features
Secure Hash Algorithm Cryptoprocessor Core
SHA-1
Features
Security Protocol Accelerators provide increased performance, ease-of-use, and advanced security features
dwc_security_protocol_accelerators
Features
SENT/SAE J2716 Controller Core
CSENT
Features
SERDES
Features
Serial ATA
Features
Serial ATA 1.5/3.0 Gbps PHY
Features
Serial ATA Device IP Core
Features
Serial ATA Host IP Core
Features
Serial ATA I/II Device Controller IP Core
Features
Serial ATA I/II Host Controller IP Core
Features
Serial ATA IP - Device Controller
Features
Serial ATA IP - Host Controller
Features
Serial Flash Memory Model
Features
Serial Front Panel Data Port (sFPDP)
Features
Serial Peripheral Interface Master/Slave Core
QSPI-APB
Features
Serial Peripheral Interface VIP
Features
Serial RapidIO IP Core
Features
Serial RapidIO to AHB Interface IP Cores
Features
Serial RapidIO x1 and x4 Endpoint Cores
Features
Serial RapidIO-to-PCIe Intelligent Bridge IP Core
Features
Serial SCSI / SAS Verification IP
Features
Serializer/Deserializer (SERDES) IP
SESAME uHD 65 nm
SGC21300 VREF - Very High PSRR Low Quiescent Band Gap
Features
SGC21300 VREF - Very High PSRR Low Quiescent Band Gap
Features
SGC21303 VRE-- Voltage Reference Nano Power Series
Features
SGC21510 OSC - Crystal Oscillator Nano Power Series
Features
SGC2185X Led Driver - Digitally Programable Low Dropou
Features
SGC62 DC/DC Buck - Ultra Low Quiescent Series
Features
SGC62XXX DC/DC Buck - Ultra Low Quiescent Series
Features
SGC66XXX DC/DC Buck-Boost - Multiple Output Ultra Low IQ Series
Features
SGC67 DC/DC Buck - Ultra Fast Response High Power Series
Features
SGC73 LDO - Low Noise High PSRR Series
Features
SGC73XXX LDO - Low Noise High PSRR Series
Features
SGIO IO T040G-LVCMOS18 CUP, LVCMOS18 ATB CUP 1.8 V Bidirectional LVCMOS with Programmable Schmitt Trigger, Drive & Pull-Up/Down
Features
SGIO IO T040G-LVCMOS25 CUP 2.5 V Bidirectional LVCMOS with Programmable Schmitt Trigger, Drive & Pull-Up/Down
Features
SGIO IO T040G-LVCMOS33 CUP, LVCMOS33 ATB CUP 3.3 V Bidirectional LVCMOS with Programmable Schmitt Trigger, Drive & Pull-Up/Down
Features
SGIO IO T040G-LVDS18 RX CUP, LVDS18 RX TERM CUP 1.8 V, 800 MHz LVDS Reciever With andWithout Input Termination
Features
SGIO IO T040G-XTAL18 CUP 1.8 V, 40 MHz Crystal Oscillator with Programmable Drive & Limiter Resistor
Features
SGIO IO T040GP-LVDS18 TX CUP, LVDS18 VREF CUP 1.8 V, 675 MHz LVDS Transmitter
Features
SGIO IO T065GP-DD2_CUP 1.8 V, DDR2 With andWithout Input Termination
Features
SGIO IO T065GP-THERMAL DIODE
Features
SGIO IO T065GP-XTAL33_CUP - 2.5 / 3.3 V, 40 Mhz Crystal Oscillator
Features
SGIO_IO_T065GP-ANALOG_PADS-Analog I/O Pads with and without ESD Protection
Features
SGIO_IO_T065GP-LVDS33_RX_CUP - 3.3 V, 750 MHz LVDS Reciever
Features
SGIO_IO_T065GP-LVDS33_TERM_RX_CUP - 3.3 V, 750 MHz LVDS Reciever with Input Termination
Features
SGIO_IO_T065GP-LVDS33_TX_CUP - 3.3 V, 675 Mhz LVDS Transmitter
Features
SGIO_IO_T065GP-LVTTL33_ATB_CUP - 2.5 / 3.3 V Bidirectional LVTTL I/O combined with Analog Test Bus (ATB)
Features
SGIO_IO_T065GP-LVTTL33_CUP - 2.5 / 3.3V Bidirectional LVTTL I/O with Programmable Drive, Schmitt Trigger & Pull-Up/Down
Features
SGIO_IO_T065GP-LVTTL33_OD_CUP - 2.5 / 3.3 V Bidirectional LVTTL Input and Open Drain Output
Features
SGIO_IO_T065GP-POWER - I/O & Core Power Pads Along with Power-down Detector
Features
SGMII PCS
Features
SGX Series5 Graphics
Features
SGX Series5XT
Features
SH-4 32-bit RISC CPU Core Family
Features
SH-5 CPU core family
Features
SH1636 SERDES Gigabit Ethernet Transceivers, VITAL Model
Features
SHA-1 Fast IP Core (Altera)
Features
SHA-1 Fast IP Core (Xilinx)
Features
SHA-1 hashing cores
Features
SHA-1 IP Core
Features
SHA-256
Features
SHA-256 Fast IP Core (Altera)
Features
SHA-256 Fast IP Core (Xilinx)
Features
SHA-3 Secure Hash Function Core
SHA-3
Features
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Displaying 3101-3200/5348
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers



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