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 Search Result 
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Displaying 101-120/120

RS Enc
Features
RS Enc / Dec
Features
RS Encoder-Decoder IP Core
Features
RS(255, 239) with Erasures
Features
SkyPHY™ DVB-S2 Receiver ASIC (ECC3100)
Features
TPC Cores (TC3400)
Features
Trellis Decoder; 67,500 gates typical (user parameterised design), size and max clock depends on technology and parameters.
VA08V
Features
VITDEC11NR - 802.11n / 802.11ac Viterbi Decoder
Features
Viterbi Dec
Features
Viterbi Encoder/Decoder; 2,000 to 40,000 gates typical (user parameterised design), size and max clock depends on technology and parameters.
Viterbi eSi-7590
Features
Viterbi K=7 decoder for 802.16m
Features
Viterbi K=7 decoder for LTE (3GPP - Long Term Evolution)
tb_vit_dec7_lte
Features
Viterbi K=7 tail-biting decoder for WiMAX
tb_vit_dec7
Features
WiMAX (TC4200-WiMAX)
Features
XCO2EFEC4 10G G975.1 I.4 Enhanced FEC Core
Features
XCO2EFEC7 10G G975.1 I.7 Enhanced FEC Core
Features
XCO3EFEC4– G975.1 I.4 Enhanced FEC Core
Features
XCO3FECD
Features
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Displaying 101-120/120
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers



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