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 Search Result 
Displaying 1-36/36

12-format video decoder including HEVC/H.265 4Kp60
CS8140 Malone HEVC/H.265 multi-format video decoder
Features
4-lane V-by-One Serializer TSMC 40nm LP
SERVBY1TS40LP
Features
An essential suite of interoperating IP modules for thoroughly protecting SoCs, with relatively easy deployment and sharing of enc
GEON Security Platform
Features
Avalon MM Pipeline Bridge
AVC/H.264 video decoder core for SoC implementation
CS8110 AVC/H.264 Video Decoder
Features
AVC/H.264 video encoder core
CS9910 AVC/H.264 video encoder
Features
Bluetooth 5.2 Dual Mode RF IP - 22nm - The Ultra-Low-Power DM RF transceiver IP is designed to meet 2.4 GHz standards
Bluetooth 5.2 Dual Mode RF IP - 22nm
Features
Combined HEVC & AVC video decoder core for SoC implementation
CS8130 HEVC & AVC Video Decoder
Features
Core Voltage De-Skew PLL 5nm to 40nm
Features
Core Voltage De-Skew PLL TSMC 16nm FF+C
PLLTS16FFCLVDESKEWB
Features
DMAC
Features
DP80390
Features
DP80390XP
Features
EVB for IEEE 1588 Boundary, Slave and Master Clock
IPC500
Features
EVB-Demo Equipment for IEEE 1588 Boundary, Slave and Master Clock
IPC600
Features
Fractional-N Synthesizer TSMC, SMIC, GF, Samsung 5nm to 16nm
Features
Fully Customizable Display Controller IP supporting the OpenWF display API specification
CDC 200 – Configurable Display Controller IP
Features
HEVC/H.265 4Kp120 enhanced frame rate video decoder
CS8150 HEVC/H.265 4Kp120 video decoder
Features
HEVC/H.265 4Kp60 video decoder core for SoC implementation
CS8120 HEVC/H.265 4Kp60 Video Decoder
Features
HEVC/H.265 8Kp60 enhanced resolution video decoder core
CS8160 HEVC/H.265 8Kp60 video decoder
Features
IEEE 1588 Boundary, Slave and Master Clock - Chip on FPGA
IPC9000
Features
IEEE 1588 Boundary, Slave and Master Clock - Chip on FPGA
IPC9100
Features
IEEE 1588 Boundary, Slave and Master Clock – IP Core
IPC9010
Features
IEEE 1588 Slave Clock - Chip on FPGA
IPC1603
Features
IEEE 1588 Slave and Master Clock - Chip on FPGA
IPC1710
Features
IPC9011 IEEE 1588 Boundary, Slave and Master Clock – IP Core
IPC9011
Features
Level-2 Cache plus Memory Tracker Technology
L2+ Cache
Features
Low Bandwidth Integer PLL 5nm to 180nm
Features
Master I3C bus controller with FIFO
DI3CM-FIFO
Features
Memory Request Optimizer
MRO
Features
Multi-constellation GNSS IP supporting GPS, GALILEO, GLONASS, BeiDou3, QZSS, IRNSS, SBAS.
GNSS Digital IP
Features
Multi-format video decoder including HEVC/H.265 & VP9 4Kp60
CS8141 Malone HEVC & VP9 multi-format video decoder
Features
Programmable Fractional PLL TSMC 7nm FF
PLLTS7FFFRACE
Features
Royalty-free and fully scalable 32-bit RISC CPU
D32PRO
Features
Silicon based supercap provides a 2X increase in effective capacitance and dynamic power reduction in mixed signal,digital, and switching systems
CC_100IP
Features
SoC and IP
Displaying 1-36/36
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