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 Search Result 
Displaying 201-300/332

Memory Compilers & Specialty Memory
TSMC 28HP
Features
Memory Compilers & Specialty Memory
TSMC 16LL
Features
Memory Request Optimizer
MRO
Features
Memory Test & Repair
Features
Memory Test Core
Features
Metal Programmable ROM16kx8 in 0.35µm CMOS (C35/S35)
Features
Microprocessor Debug Module (MDM)
Features
MIPI UniProSM Software Stack
Moble DDR SDRAM Memory I/F IP mDDRC 333A
Features
Multi Channel SDR SDRAM Memory Controller
Features
Multi-Channel-OPB (MCH_OPB) SDRAM Controller
Features
Multi-Channel-OPB_DDR2_Controller
Features
Multi-Channel-OPB_DDR_Controller
Features
Multi-Channel-OPB_EMC_Controller
Features
Multi-Port AHB DDR-SDRAM controller
BA312
Features
Multi-Port Register Files, SRAM HD Memory, and OTP Memory in a single highly- optimized solution
Memory
Features
Multi-Port_Front-End
Features
NOVeA
Novelics coolCAM™
Features
Novelics coolREG™
Features
Novelics coolROM™
Features
Novelics coolSRAM-1T™
Features
Novelics coolSRAM-6T™
Features
Novelics coolSRAM-8T™
Features
ntINT_DEINT
ntINT_DEINT
Features
NVM OTP in Dongbu (180nm, 150nm)
dwc_nvm_otp_dongbu
Features
NVM OTP in Fujitsu (90nm, 65nm, 55nm)
dwc_nvm_otp_fujitsu
Features
NVM OTP in GlobalFoundries (65nm, 55nm, 40nm, 28nm, 22nm)
dwc_nvm_otp_globalfoundries
Features
NVM OTP in SMIC (180nm, 110nm, 65nm, 55nm, 40nm)
dwc_nvm_otp_smic
Features
NVM OTP in Tower (180nm)
dwc_nvm_otp_tower
Features
NVM OTP in TSMC (180nm, 130nm, 110nm, 90nm, 65nm, 55nm, 40nm, 28nm, 16nm)
dwc_nvm_otp_tsmc
Features
NVM OTP in UMC (180nm, 110nm, 90nm, 80nm, 55nm, 40nm)
dwc_nvm_otp_umc
Features
On-Chip FIFO Memory
Op-Amps
Op-Amps
Features
OPB BRAM Interface Controller
Features
OPB DDR SDRAM Controller
Features
OPB External Memory Controller (EMC)
Features
OPB HWICAP
Features
OPB Interrupt Controller
Features
OPB SDRAM Controller
Features
OPB SYSACE Interface Controller
Features
PCI Express AXI DMA Back-End Core
AXI DMA Back-End Core
Features
PCI Express DMA Back-End Core
DMA Back-End Core
Features
PCI Express DMA Back-End Driver
DMA Driver
Features
PCI Express DMA Driver
Expresso DMA Driver
Features
PCIe 4.0 PHY IP with 16GT/s optimized for low power consumption (Silicon Proven in TSMC 12FFC)
PCIe 4.0 SerDes PHY IP
Features
PCIe 5.0 PHY IP with 32GT/s optimized for low power consumption (Silicon Proven in TSMC 12FFC)
PCIe 5.0 SerDes PHY IP
Features
PE-NFC --ONFI 2.2 Nand Flash Controller
Features
PE-NFC 3.0 --ONFI 3.0 Nand Flash Controller
Features
PE-QSFC -- Quad Serial Flash Controller
Features
PE-SDIO3.0 -- SDIO 3.0 Device Controller
Features
PE-SDMMCD -- SD 3.0 / eMMC 4.51 Device Controller
Features
PE-SFC-ECC - Serial Flash Controller with ECC
Features
PE-SMID -- SD3.01/SDIO 3.0/eMMC 4.51 Device Controller
Features
PE-SMIH -- SD3.01/SDIO 3.0/eMMC 4.51 Host Controller
Features
PLB BRAM Interface Controller
Features
PLB DDR SDRAM Controller
Features
PLB DDR2 Controller
Features
PLB External Memory Controller (EMC)
Features
PLB SDRAM Controller
Features
PPROM 16x8 / 4x8
Features
QDRII / II+ SRAM Controller with UniPHY
Features
QDRII SRAM Controller
Features
RDRAM
Features
Read-Modify-Write Core
Features
RENAISSANCE 10X
RENAISSANCE 2X
RENAISSANCE 4X
RENAISSANCE FOR DATACOM
Features
Reorder Core
Features
ROM in 0.8 µm CMOS
Features
RSCODECOTU2- RS CODEC supporting OTU1 / OTU2
Features
RSECODEC
Features
S13_HSRASP_01---VeriSilicon SMIC 0.13μm High-Speed Synchronous Single-Port SRAM compiler
Features
S13_LPVROM_01---VeriSilicon SMIC 0.13um Syn. LP VROM Compiler
Features
S13_ULPRASP_01---VeriSilicon SMIC 0.13μm Ultra-Low-Power Synchronous Single-Port SRAM compiler
Features
S13_VROM_01---VeriSilicon SMIC 0.13μm Synchronous programmable Via1 ROM compiler
Features
S13LL_HDRASP_02---VeriSilicon SMIC 0.13μmLL 1P3M High-Density Synchronous Single-Port SRAM compiler
Features
S3000
Features
Scatter Gather DMA Controller
SD 3.0 / eMMC 4.51 Host Controller
Features
SD 3.0 Device Controller
Features
SD/SDIO 3.0 Device COMBO Controller
Features
SD/SDIO 6.0 Device Controller IP
SDIO Device Controller IP
Features
SD/SDIO 6.0 Host Controller IP
SDIO Host Controller IP
Features
SD/SDIO Device IP Core
Features
SD/SDIO/MMC Target IP
Features
SD3.0 / eMMC 5.0 Hardware Validation Platform
Features
SD4 / eMMC 5.0 Hardware Validation Platform
Features
SD4.0 / SDIO4.0 / eMMC4.51 Host Controller IP
Features
SDRAM
Features
Serial ATA 1.5/3.0 Gbps PHY
Features
Serial Flash Memory Model
Features
Serial Peripheral Interface (SPI)
Features
SHS is an automated hierarchical test solution for efficiently testing system-on-chips (SoCs) or designs using multiple IP/cores
dwc_star_hierarchical_system
Features
Silicon Proven on a customer SOC - DDR4 Combo PHY supporting DDR3L, DDR3U, LPDDR3, LPDDR2
OMNI_DDR4_TSMC28
Features
SiWare™ Memory
SlimChip IP
Features
SMIC18_VROM_01
Features
SMIC18LL_LPVROM_01---VeriSilicon SMIC 0.18um LL Pro Syn. LP VROM Compiler
Features
Displaying 201-300/332



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