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AHB-MLIC - AHB Multilayer Interconnect
Features

Arria V Hard IP for PCI Express
Features

Avalon MM Clock Crossing Bridge

Avalon MM Master Agent

Avalon MM Master BFM

Avalon MM Master BFM w/Avalon ST API Wrapper

Avalon MM Master Translator

Avalon MM Pipeline Bridge

Avalon MM Tristate Bridge

Avalon ST Data Format Adapter

Avalon ST Error Adapter

Avalon ST Idle Inserter

DDR3 SDRAM Controller for UniPHY
Features

High-Performance DDR3/3L Memory Controller
S3C-DDR40-HPC
Features

Interlaken, 100G for 28nm devices

Interlaken, 100G, 12 Lanes

Interlaken, 100G, 20 Lanes

Interlaken, 150G, 24 Lanes

Interlaken, 40G, 8 Lanes

Interlaken, 50G for 28nm devices

Interlaken-PHY (ILKN-PHY)
Features

IP Compiler for PCI Express (Hard IP)
Features

IP Compiler for PCI Express x1 (Soft IP)
Features

IP Compiler for PCI Express x4 (Soft IP)
Features

IP Compiler for PCI Express x8 (Soft IP)
Features

IRQ Clock Crosser

Memory Request Optimizer
MRO
Features

Mentor Graphics AXI Verification IP Suite - Altera Edition
Features

PCI Compiler, 32-bit Master/Target
Features

PCI Compiler, 64-bit Master/Target

PCI-DHB-AHB - AMBA AHB Device/Host Bridge Core
Features

PCIe 4.0 Controller IP supporting Root Complex, End Point, Switch Port compliant with PCIe 4.0/3.0/2.0/1.0 and fully synthesizable
PCIe 4.0 Controller IP
Features

PCIe 4.0 PHY IP with 16GT/s optimized for low power consumption (Silicon Proven in TSMC 12FFC)
PCIe 4.0 SerDes PHY IP
Features

RLDRAM II Controller
Features

Silicon based supercap provides a 2X increase in effective capacitance and dynamic power reduction in mixed signal,digital, and switching systems
CC_100IP
Features

SPI Slave to Avalon Master Bridge

Stratix V Hard IP for PCI Express
Features

Triple Speed Ethernet with 1588
Features

UDPIP-40G/50G - UDP/IP Hardware Protocol Stack
Features

USB 3.1 Gen1 / Gen2 Device Controller IP
USB 3.1 Device Controller IP
Features

USB 3.1 Gen1 / Gen2 Host Controller IP
USB 3.1 Host Controller IP
Features

USB 3.1 Gen1 / Gen2 Hub Controller IP
USB 3.1 Hub Controller IP
Features

USB 3.1 PHY IP ((10G/5G),Silicon proven in TSMC 28HPC+)
USB 3.1 Gen1 Gen2 PHY IP
Features

USB 3.2 Gen1 / Gen2 Device Controller IP
USB 3.2 Device Controller IP
Features

USB 3.2 OTG High / Full / Low- Speed Dual Role IP Core
USB 3.2 OTG Controller IP
Features

USB 4.0 Device Controller IP Core for 40Gbps performance
USB 4.0 Device Controller IP
Features

USB 4.0 Host Controller IP Core for 40Gbps performance
USB 4.0 Host Controller
Features

USB 4.0 Hub Controller IP Core for 40Gbps performance
USB 4.0 Hub Controller IP
Features

Displaying 1-48/48