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Short Desc. : 10GBase-KR PHY
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Altera provides a complete 10 Gbps Ethernet over backplane 10GBASE-KR physical coding sublayer (PCS), and physical media attachment (PMA) sublayer intellectual property (IP) known as PHY IP. This IP is designed to the IEEE 802.3ap (2007) Ethernet over backplane standard. Altera's 10GBASE-KR PHY MegaCore® function enables Ethernet connectivity at 1 Gbps and 10 Gbps (1G/10GbE) over system chassis copper backplanes. This interface PHY can be implemented in Altera® devices with integrated serial transceivers operating above 10.3125 Gbps and supporting backplanes.

Stratix® V and Arria® V GZ FPGAs provide fully integrated and silicon-proven 1G/10Gb Ethernet serial transceivers for interfacing to backplanes. Altera's 10GBASE-KR PHY IP core is composed of the 1Gb and 10Gb Ethernet serial transceiver hard IP, and soft IP including auto-negotiation (AN), link training (LT), foward error correction (FEC), 1 GIGE PCS, sequencer, control registers, and status registers for PHY management. The 10GBASE-KR PHY IP can be used for single to multiport backplane interface applications for performance scalability. Altera has developed and tested in hardware the combined 1G/10Gb Ethernet Media Access Controller (MAC) and 10GBASE-KR PHY design example.

The 10GBASE-KR PHY IP uses built-in transceivers in the Altera device, that saves system cost, board space, and the power required for an external 10GBASE-KR serializer/deserializer (SERDES) device. Figure 1 shows the 10GBASE-KR PHY high-level block diagram.

Figure 1. 10GBASE-KR PHY Block Diagram Figure 1. 10-Gigabit Ethernet MAC with 10GBASE-R PHY and serial 10-Gbps XFI or SFI interface Block Diagram

Easy to Use

  • Complete 10GbE 10GBASE-KR PHY solution available to start your design quickly
  • Configuration and generation by the Altera MegaWizardTM Plug-In Manager parameter editor

Robust Solution

  • Designed to IEEE 802.3ap 2007 10GBASE-KR Ethernet over backplane standard
  • Validated in simulation and in hardware

Protocol Solution

Performance

Typical expected performance and resource utilization figures for this IP core are provided in the Altera Transceiver PHY IP Core User Guide (PDF).


Features :
  • Integrated 1000BASE-KX / 10GBASE-KR (1G/10Gb) backplane Ethernet PCS and PMA
  • Direct internal interface with Altera 1G/10GbE MAC for a complete single-chip solution
  • 10GBASE-KR auto-negotiation (AN) for negotiating between 1000BASE-KX (1 Gbps Ethernet or 1GbE) and 10GBASE-KR (10 Gbps Ethernet or 10GbE) PHY types per clause 73 of the IEEE 802.3ap-2007 standard
  • Link training (LT) to automatically configure the remote link partner transmitter PMD for the lowest bit error rate (BER) per clause 72 of IEEE 802.3ap-2007 standard
  • Forward error correction (FEC) to minimize retransmission in accordance to IEEE 802.3 and 802.3ba clause 74
  • Internal programmable algorithm for the receiver adaptation process per IEEE 8023.ap clause 72.6.10.2.3 for ease of use
  • Flexible IP user controls for performance optimization in various system configurations and channels
  • Receiver-link fault status detection
  • Local serial loop-back from transmitter to receiver at the serial transceiver for self test
  • High-performance internal system interfaces
    • GMII and single data rate (SDR) XGMII interfaces to 1G/10GbE MAC, 8 bits at 125 MHz and 72 bits at 156.25 MHz respectively for data transfer
    • Altera Avalon® Memory-Mapped (Avalon-MM) 32 bit interface for slave management

Categories :
Portability :
 FPGA Technologis 
Altera :
ARRIA V GZ
STRATIX V GT
STRATIX V GX

Type : Hard
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL
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