Altera provides a complete 10 Gbps Ethernet over backplane 10GBASE-KR physical coding sublayer (PCS), and physical media attachment (PMA) sublayer intellectual property (IP) known as PHY IP. This IP is designed to the IEEE 802.3ap (2007) Ethernet over backplane standard. Altera's 10GBASE-KR PHY MegaCore® function enables Ethernet connectivity at 1 Gbps and 10 Gbps (1G/10GbE) over system chassis copper backplanes. This interface PHY can be implemented in Altera® devices with integrated serial transceivers operating above 10.3125 Gbps and supporting backplanes.
Stratix® V and Arria® V GZ FPGAs provide fully integrated and silicon-proven 1G/10Gb Ethernet serial transceivers for interfacing to backplanes. Altera's 10GBASE-KR PHY IP core is composed of the 1Gb and 10Gb Ethernet serial transceiver hard IP, and soft IP including auto-negotiation (AN), link training (LT), foward error correction (FEC), 1 GIGE PCS, sequencer, control registers, and status registers for PHY management. The 10GBASE-KR PHY IP can be used for single to multiport backplane interface applications for performance scalability. Altera has developed and tested in hardware the combined 1G/10Gb Ethernet Media Access Controller (MAC) and 10GBASE-KR PHY design example.
The 10GBASE-KR PHY IP uses built-in transceivers in the Altera device, that saves system cost, board space, and the power required for an external 10GBASE-KR serializer/deserializer (SERDES) device. Figure 1 shows the 10GBASE-KR PHY high-level block diagram.
Figure 1. 10GBASE-KR PHY Block Diagram
Easy to Use
- Complete 10GbE 10GBASE-KR PHY solution available to start your design quickly
- Register transfer level (RTL) and post-fit functional simulation for Altera supported Verilog HDL and VHDL simulators
- 1G/10GbE MAC and 10GBASE-KR PHY verification testbench and design example
- Development board
- Configuration and generation by the Altera MegaWizardTM Plug-In Manager parameter editor
- Designed to IEEE 802.3ap 2007 10GBASE-KR Ethernet over backplane standard
- Validated in simulation and in hardware
Typical expected performance and resource utilization figures for this IP core are provided in the Altera Transceiver PHY IP Core User Guide (PDF).