This user guide describes the IP cores provided by Altera that are included in the Quartus® II design software.
The IP cores are optimized for Altera® devices and can be easily implemented to reduce design and test time. You can use the IP parameter editor from Qsys or SOPC Builder to add the IP cores to your system, configure the cores, and specify their connectivity
Qsys is a system-level integration tool which is included as part of the Quartus II software. Qsys leverages the easy-to-use interface of SOPC Builder and provides backward compatibility for easy migration of existing embedded systems.You can implement a design using the IP cores from the Qsys component library.
All the IP cores described in this user guide are supported by Qsys except for the following cores which are only supported by SOPC Builder.
- Common Flash Interface Controller Core
- SDRAM Controller Core (pin-sharing mode)
- DMA Controller Core
For more information on Qsys or SOPC Builder, refer to Volume 1: Design and Synthesis of the Quartus II Handbook or SOPC Builder User Guide
The IP cores described in this user guide support all Altera device families except the cores listed in Table 1–1
Table 1–1. Device Support
|EPCS Serial Flash Controller Core
||All device families except HardCopy® series.
|Cyclone III Remote Update Controller Core
||Only Cyclone III device.
||Only Stratix® IV GX and Stratix IV GT devices.
|On-Chip FIFO Memory Core
||All device families except HardCopy® series.
|Avalon ALTPLL Core
||All device families except Stratix V, Cyclone V, and Arria V device families.
Note: Different device families support different I/O standards, which may affect the ability of the core to interface to certain components. For details about supported I/O types, refer to the device handbook for the target device family.
The following IP cores are scheduled for product obsolescence and discontinued support.
- PCI Lite Core
- Mailbox Core
Altera recommends that you do not use these cores in new designs.
Note: For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.
Document Revision History
The following table shows the revision history for this document.
||â– Removed System ID core from the list of cores which are only supported by SOPC Builder. â– Converted the document to new frame template version 2.0 and made textual and style changes.
Section I. Off-Chip Interface Peripherals
This section describes the interfaces to off-chip devices provided for SOPC Builder systems.
SDRAM Controller Core
The SDRAM controller core with Avalon® interface provides an Avalon Memory-Mapped (Avalon-MM) interface to off-chip SDRAM. The SDRAM controller allows designers to create custom systems in an Altera® device that connect easily to SDRAM chips. The SDRAM controller supports standard SDRAM as described in the PC100 specification.
SDRAM is commonly used in cost-sensitive applications requiring large amounts of volatile memory. While SDRAM is relatively inexpensive, control logic is required to perform refresh operations, open-row management, and other delays and command sequences. The SDRAM controller connects to one or more SDRAM chips, and handles all SDRAM protocol requirements. Internal to the device, the core presents an Avalon-MM slave port that appears as linear memory (flat address space) to Avalon-MM master peripherals.
The core can access SDRAM subsystems with various data widths (8, 16, 32, or 64 bits), various memory sizes, and multiple chip selects. The Avalon-MM interface is latency-aware, allowing read transfers to be pipelined. The core can optionally share its address and data buses with other off-chip Avalon-MM tri-state devices. This feature is valuable in systems that have limited I/O pins, yet must connect to multiple memory chips in addition to SDRAM.
The SDRAM controller core with Avalon interface is SOPC Builder-ready and integrates easily into any SOPC Builder-generated system. This chapter contains the following sections:
Figure 1–1 shows a block diagram of the SDRAM controller core connected to an external SDRAM chip.
Figure 1–1. SDRAM Controller with Avalon Interface Block Diagram
The following sections describe the components of the SDRAM controller core in detail. All options are specified at system generation time, and cannot be changed at runtime.
The Avalon-MM slave port is the user-visible part of the SDRAM controller core. The slave port presents a flat, contiguous memory space as large as the SDRAM chip(s). When accessing the slave port, the details of the PC100 SDRAM protocol are entirely transparent. The Avalon-MM interface behaves as a simple memory interface. There are no memory-mapped configuration registers.
The Avalon-MM slave port supports peripheral-controlled wait states for read and write transfers. The slave port stalls the transfer until it can present valid data. The slave port also supports read transfers with variable latency, enabling high-bandwidth, pipelined read transfers. When a master peripheral reads sequential addresses from the slave port, the first data returns after an initial period of latency. Subsequent reads can produce new data every clock cycle. However, data is not guaranteed to return every clock cycle, because the SDRAM controller must pause periodically to refresh the SDRAM.
Note: For details about Avalon-MM transfer types, refer to the Avalon Interface Specifications
More detailed information can be found here...