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The Altera® DDR and DDR2 SDRAM High-Performance Controller MegaCore® functions provide simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM. The MegaCore functions work in conjunction with the Altera ALTMEMPHY physical interface megafunction. The controllers offer a half-rate interface and a full-rate interface to the customer application logic. For exact device support, please refer to the user guide.
The MegaWizard Plug-In Manager generates an example design, instantiates a phase-locked loop (PLL), an example driver, your DDR or DDR2 SDRAM controller custom variation, and an optional DLL (for Stratix® series FPGAs only). The example design is a fully functional design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals. Figure 1 shows a system-level diagram including the example design that the DDR or DDR2 SDRAM Controller MegaCore functions create for you.
Figure 1. DDR2 SDRAM High-Performance Controller System-Level Diagram
Use the Altera OpenCore Plus Evaluation flow to test drive this MegaCore function.
Typical expected performance and utilization figures for this MegaCore function are provided in the DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide (PDF).
Altera awards the I-Tested certification to MegaCore functions or Altera Megafunction Partners Program (AMPPSM) IP cores that have been verified in an Altera FPGA, on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the relevant protocols.
For technical support on this MegaCore function, please visit the Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.