Short Desc. : DXAUI PHY
Overview :
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As the leading provider of 10 Gbps Ethernet (10GbE) for FPGA devices, Altera offers the XAUI PHY MegaCore® function intellectual property (IP) core for you to easily build systems with a very high throughput Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera® device to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module.

You can implement the XAUI PHY (excluding the PHY management functions) in hard silicon in Altera Stratix® IV (GX and GT), Stratix II GX, Arria® II GX, and Cyclone® IV GX FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. XAUI PHY can also be implemented in soft IP form in Stratix® V , Stratix IV, Arria V, and Cyclone V FPGAs with serial transceivers. Additionally, for applications requiring 20 Gbps throughput, Altera's XAUI PHY solution can support DXAUI (4x 6.25 Gbps) implementations on Stratix IV (GX and GT) FPGAs. Figure 1 illustrates an example of XAUI PHY in Altera devices.

Figure 1. XAUI PHY in an Altera Device

Figure 1. XAUI PHY in an Altera Device


  1. XAUI PCS is implemented in hard logic in Altera devices with serial transceivers. It can also be implemented in soft IP in Stratix V, Stratix IV, Arria V, and Cyclone V FPGAs with serial transceivers
  2. SDR XGMII = single data rate XGMII, 72 bits at 156.25 Mbps

Easy to Use

  • Complete 10G Ethernet (XAUI) PHY solution available to start your design quickly
    • RTL and post-fit functional simulation for Altera supported Verilog HDL and VHDL simulators
    • Verification testbench and design example
    • Development boards
  • Configuration and generation by Altera MegaWizardTM Plug-In Manager parameter editor

Robust Solution

  • IEEE 802.3 10GbE standard-compliant, Clauses 46, 47, and 48
  • Extensively validated in simulation and in hardware with standard 10GbE tester

Protocol Solution


Typical expected performance and resource utilization figures for this IP core are provided in the XAUI PHY Resource Utilization and Performance (PDF).

Features :
  • Complete 10G Ethernet (XAUI) PHY solution for 4 x 3.125 Gbps serial external interface
  • PHY consisting of 10GBASE-X physical coding sublayer (PCS), physical medium attachment (PMA), XGMII Extender Sublayer (XGXS), 10G Ethernet (XAUI), and PHY management functions
  • Direct interface with Altera's 10GbE MAC for a complete solution
  • Direct standard XAUI PHY (4 x 3.125 Gbps) connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, backplane, and short cable applications
  • PHY integrated into hard silicon in Altera devices with serial transceivers above 3 Gbps; also soft XAUI PCS available in Stratix IV, Stratix V, and Arria V FPGAs with serial transceivers
  • Dynamic partial reconfigurable I/O (DPRIO) support in serial transceivers to adapt to various XAUI channel characteristics and devices in systems during operation
  • Implementing the Ethernet-standard XAUI PHY functions: data and control bits 8b/10b encoding/decoding and per-lane synchronization, data serialization/deserialization (SERDES) to and from 4 x 3.125 Gbps line, receiver four-data lane alignment, deskew, and alignment of four lanes, and receiver rate matching for clock frequency compensation
  • Local serial loopback from transmitter to receiver at the device's serial transceiver for self testing
  • High-performance internal system interfaces
  • DXAUI (4 x 6.25 Gbps) support for Stratix IV (GX and GT) FPGAs

Categories :
Portability :
 FPGA Technologis 
Altera :

Type : Hard

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