These popular PCIe MegaCore® functions (x1, x4, or x8 lane configurations) support all memory, I/O, configuration, and message transactions. The MegaCore functions have an optimized application interface to achieve maximum effective throughput. The MegaCore functions are also flexible and configurable, allowing customization for your specific needs. For example, the MegaCore functions support a configurable payload and a configurable retry buffer, and provide optional support for high-reliability features, such as ECRC and AER.
Altera has performed significant hardware testing of the PCIe x1, x4, and x8 endpoints to ensure a reliable solution. These MegaCore functions have been tested internally with a variety of x86 motherboards, PCIe switch chips, and embedded microprocessors. Additionally, the soft IP MegaCore functions were tested at the PCI-SIG compliance workshops and passed with high quality results, including a 100 percent passing rate for the PCI-SIG® gold tests.
Figure 1 shows a high-level block diagram of the PCIe soft IP block with the Avalon-ST interface.
Figure 1. PCIe Soft IP Block Diagram
Additional Information and Resources
The following resources are available for you to easily adopt PCIe into your design:
- Complete and detailed documentation of the IP core
- Complete description of the FPGA capabilities
- Reference designs to jump start system-level design
- Complementary partner solution
Please contact an Altera sales representative to get a complete list of platforms tested for compliance checking at PCI-SIG
Resource Utilization and Performance
Estimated resource utilization and performance figures for this core are provided in the IP Compiler for PCI Express User Guide (PDF).