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 Altera 
Short Desc. : RapidIO, Gen 1, x1 and x4
Overview :
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OpenCore Plus Support
SOPC Builder Ready
I-Test
Qsys Compliant



The RapidIO® standard was adopted by a significant portion of the wireless industry as a high-speed interconnect and is typically used between digital signal processors and between the control plane processors and memory. RapidIO is also gaining acceptance as a backplane interconnect due to its adoption of widely used standards for the electrical characteristics of the physical media attachment (PMA) such as XAUI or CEI for up to 6.25 Gbaud data rate.

Altera Offers Two Distinct RapidIO MegaCore Functions

  • RapidIO II MegaCore® Function complies with the RapidIO Specification Revision 2.2
    • Physical, transport, and logical layer separations (modular architecture)
    • IDLE2 sequence - long control symbol
    • 1.25, 2.5, 3.125, 5.0 and 6.25 Gbaud lane rates with 1x, 2x, and 4x link widths
  • RapidIO MegaCore Function complies with the RapidIO Specification Revisions 1.3 / 2.1
    • Physical, transport, and logical layer separations (modular architecture)
    • IDLE1 sequence - short control symbol
    • 1.25, 2.5, 3.125, and 5.0 Gbaud lane rates with 1x and 4x link widths

For device support details, such as lane rates, link widths, and speed grades, refer to the RapidIO MegaCore function user guides.

For a system-level integration-ready solution, you can save several months of design time by selecting all RapidIO layers—including features such as address translation and simple Avalon® Memory-Mapped (Avalon-MM) and Avalon Streaming (Avalon-ST) FIFO interfaces.

Protocol Solution

Figure 1 shows an example of a system built using Qsys Builder with a Nios® II soft embedded processor as a processing element. The program memory can include “boot code” for system-level enumeration of the various end points and also configure the capability address registers of the endpoints and the MegaCore function.

Figure 1. A Complete SRIO System

Figure 1. A Complete SRIO System


Features :
  • PHY based on embedded transceivers
  • Easy to use
    • MegaWizardTM Plug-In Manager GUI allows easy manual optimization of parameters, such as interface FIFO depths, address translation windows, and output differential voltage and pre-emphasis
    • Easy configuration provides ways to reduce resource utilization to create smaller MegaCore function variations depending on application needs
    • Qsys Altera's System Integration Tool for system interconnect
  • Robust solution

Categories :
Portability :
 FPGA Technologis 
Altera :
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V GT
CYCLONE V GX
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
Stratix II
Stratix II GX
STRATIX III E
STRATIX IV GT
STRATIX IV GX
STRATIX V E
STRATIX V GT
STRATIX V GX

Type : Hard



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