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Short Desc. : Reed Solomon Encoder / Decoder II
Overview :

 

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OpenCore Plus Support

Features and Description

The Reed-Solomon (RS) Compiler II offers a fully parameterizable RS encoder and decoder. RS encoders and decoders are widely used for error detection and correction in a wide range of digital signal processing (DSP) applications for storage, retrieval, and transmission of data. RS Compiler II is designed to support optical transport network (OTN) applications.

Throughput:

  • Supports up to 10 Gbps with multiple core instantiation
  • Provides 2.5-Gbps throughput for Stratix® series FPGAs
  • Provides 1.28-Gbps throughput for Cyclone® series FPGAs
  • Supports up to 16 interleaved channels

The RS Compiler II generates a fully parameterizable RS function, allowing you to set the following parameters:

  • Number of bits per symbol (8)
  • Number of symbols per code word (range: 204 to 255 )
  • Number of check symbols per code word (range: 2 to 66)
  • All valid field polynomials

The RS function offers the following other features:

  • Intellectual property (IP) functional simulation models for use in Altera®-supported VHDL and Verilog HDL simulators
  • Easy-to-use IP Toolbench interface:
    • Generates parameterized encoder or decoder
    • Generates customized test bench and customized Tcl script
  • Avalon®-ST interfaces
  • DSP Builder ready

IP Evaluation

Use Altera's free OpenCore Plus Evaluation feature to test drive this IP MegaCore® function.

Performance and Resource Utilization

Typical expected performance and utilization figures for this MegaCore function are provided in the Reed-Solomon Compiler II User Guide (PDF).


Categories :
Portability :
 FPGA Technologis 
Altera :
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
STRATIX III E
STRATIX IV GT
STRATIX IV GX
STRATIX V E
STRATIX V GT
STRATIX V GX

Type : Hard
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers



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