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Short Desc. : Reed-Solomon Compiler, Encoder
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Features and Description

The Reed-Solomon (RS) compiler offers a fully parameterizable RS coder and RS decoder. RS coder/decoders (CODECs) are widely used for error detection and correction in a wide range of digital signal processing (DSP) applications for storage, retrieval, and transmission of data.

The RS compiler has the following options:

  • Erasures-supporting option—the RS decoder can correct symbol errors up to the number of check symbols, if you give the location of the errors to the decoder
  • Variable encoding or decoding—you can vary the total number of symbols per codeword and the number of check symbols, in real time, from their minimum allowable values up to their selected values, when you are encoding or decoding
  • Error symbol output—the RS decoder finds the error values and location and adds these values in the Galois field to the input value
  • Bit-error output—either split count or full count

The RS Compiler generates a fully parameterizable RS function, allowing you to set the following parameters:

  • Number of bits per symbol
  • Number of symbols per codeword
  • Number of check symbols per codeword
  • Field polynomial
  • First root of generator polynomial
  • Space between roots in generator polynomial

The RS function offers the following other features:

  • Decoder features:
    • Variable option
    • Erasures-supportingoption
  • Encoder features variable architectures
  • Support for shortened codewords
  • Conforms to Consultative Committee for Space Data Systems (CCSDS) Recommendations for Telemetry Channel Coding, May 1999
  • Intellectual property (IP) functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
  • Easy-to-use IP Toolbench interface:
    • Generates parameterized encoder or decoder
    • Generates customized testbench and customized Tcl script
  • DSP Builder ready

IP Evaluation

Use Altera's free OpenCore Plus Evaluation feature to test drive this IP MegaCore® function.

Performance and Resource Utilization

Typical expected performance and utilization figures for this MegaCore function are provided in the Reed-Solomon Compiler User Guide (PDF).


Categories :
Portability :
 FPGA Technologis 
Altera :
Arria GX
ARRIA V GT
ARRIA V GX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
Stratix
Stratix GX
Stratix II
Stratix II GX
STRATIX III E
STRATIX IV GT
STRATIX IV GX
STRATIX V E
STRATIX V GT
STRATIX V GX

Type : Hard
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers



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