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Short Desc. :
I2C -- Philips Serial Bus Interface Core
I2C Bus Controller logic provides a serial interface that meets the Philips I2C bus specification and supports all transfer modes from and to the I2C bus.
The I2C logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register (i2csta) reflects the status of I2C Bus Controller and the I2C bus.
The I2C is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward.
- The I2C bus uses two wires to transfer information between devices connected to the bus: SCL (serial clock line) and SDA (serial data line).
- Master Transmitter Mode — Serial data output through SDA while SCL outputs the serial clock.
- Master Receiver Mode — Serial data is received via SDA while SCL outputs the serial clock.
- Slave Receiver Mode — Serial data and the serial clock are received through SDA and SCL.
- Slave Transmitter Mode — Serial data is transmitted via SDA while the serial clock is input through SCL.
- Data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode.
- Bi-directional data transfer.
- Own address and General Call address detection.
- 7-bit addressing format.
- Fixed data width of 8 bits.
- Data transfer in multiples of bytes.
- One-byte write and read buffer.
- HDL source or EDIF netlist, Testbench, scripts and user doc
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