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 CAST, Inc. 
Short Desc. : UDPIP-40G/50G - UDP/IP Hardware Protocol Stack
Overview :

Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming with speeds up to 40Gbps even in processor-less SoC designs. 

Trouble-free network operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a Dynamic Host Configuration Server (DHCP) server. Furthermore, the core supports 801.1Q tagging, and is suitable for operation in a Virtual LAN.    

The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or optionally via registers mapped on an SoC bus. The AMBA® AXI4-stream or the Avalon®-ST streaming protocols and the AMBA AHB and AXI, Avalon-MM, or Wishbone SoC bus protocols are supported. The core is Ethernet MAC-independent, but is available pre-integrated with a CAST, Altera, Xilinx, or other third-party eMAC core.


Features : - Complete UDP/IP Hardware Stack
- • 1/10/40G Ethernet
- • IPv4 support without packet fragmentation
- • Jumbo and Super Jumbo Frames
- • Transmit and Receive
- • ARP with Cache
- • ICMP (Ping Reply)
- • IGMP v3 (Multicast)
- • UDP/IP Unicast, and Multicast
- • UDP Port Filtering
- • UDP/IP Checksums generation and validation, and optional Ethernet CRC validation
- • VLAN (IEEE 802.1Q) support
- • 1 to 32 UDP transmit and 1 to UDP 32 receive channels
- • Ethernet Framing processing for non-UDP user-provided packets
- • DHCP client
- Trouble-Free Network Operation
- • Run time programmable network parameters:
- Local MAC address, Local IP address, Gateway IP address, and IP subnet mask
- Per channel: Destination IP address, Source and Destination and filtered UDP ports, multicast enable/disable and receive group
- • ARP support for operation in networks with Dynamic IP allocation
- Easy SoC Integration
- • Flexible interfaces:
- Packet Data: 256-bit streaming capable using Avalon-ST or AXI4-Stream
- Control/Status Registers: Generic 32-bit SRAM-like, or optionally 32-bit AHB, AXI, Avalon-MM or Wishbone
- • Separate clock domains for packet processing and control/status interfaces
- • Configurable buffer sizes
- • Rich interrupt support for system events
- • Available pre-integrated with:
- CAST, Altera, Xilinx, or other third-party 1G and 10G eMAC cores
- CAST Image and Video compression cores
Categories :
Tags : UDP/IP Protocol Stack, 40G, 50G, TCP/IP Stack, UDPIP, Hardware UDP/IP Stack Core, UDPIP, UDP
Maturity : production-proven
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria 10
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
ARRIA V GZ
ARRIA V ST
ARRIA V SX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
EP5C
FLEX 10K
HardCopy
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
HardCopy Stratix
MAX II
MAX V
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
STRATIX III E
Stratix IV
STRATIX IV E
STRATIX IV GT
STRATIX IV GX
Stratix V
STRATIX V E
STRATIX V GS
STRATIX V GT
STRATIX V GX
Lattice :
ispClock
ispMACH 4000
LatticeEC/ECP
LatticeECP2
LatticeECP2M
LatticeECP3
LatticeSC
LatticeSCM
LatticeXP
LatticeXP2
MachXO
MachXO2
Platform Manager
Power Manager II
Xilinx :
Artix-7
Kintex-7
Kintex-7 -2L
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type : Soft
Deliverables : - The core is available in synthesizable RTL and FPGA netlist forms, and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts and comprehensive user documentation.



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