True Circuits 
Part Number : TCI-TN28HPCP-DDR43PHY
Short Desc. : TSMC CLN28HPC+ 28nm DDR 4/3 PHY - 3200Mbps
Overview :

The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read data eye and gate timing are also continuously adjusted. Automatic training is included for multi-cycle read gate timing and write leveling, write data eye timing, and internal and external (on DRAM) Vref setting.

Remarkable physical flexibility allows the PHY to adapt to each customer’s die floorplan and package constraints, yet is delivered and verified as a single unit for easy timing closure with no assembly required.

The PHY is DFI 4.0 compliant, and when combined with the Northwest Logic DDR memory controller, a complete and fully-automatic DDR system is realized.

Features : - Supports DDR4-3200, DDR3/L/U, LPDDR4/X and LPDDR3, simultaneously with one hard macro
- DFI 4.0 compliant
- Supports x4, x8 and x16 DRAMs
- Up to 144 bits wide
- Up to 4 chip selects
- Incudes PLL, with frequency multiplication from low frequency reference
- Per-pin architecture, similar to a SerDes, automatically corrects skew, increases data eye and eliminates most parallel interface problems
- Continuous adjustment of read data eye and gate timing
- Automatic Training includes:
- • Multi-cycle read gate training and write leveling
- • Write data eye centering
- • Internal Vref adjustment
- • External Vref adjustment in each DRAM
- Localized and optimized PHY-to-memory controller interface to ease timing closure
- Full speed read/write BIST with pseudo-random data, mux-scan ATPG and 1149.1 Boundary Scan
- Circuitry in each pin able to measure the data eye and jitter, and calculate flight delays
Categories :
Maturity : Available on request
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

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