Part Number : dwc_mipi_dphy_globalfoundries
Short Desc. : MIPI D-PHY in GlobalFoundries (40nm, 28nm)
Overview :
The demand for advanced multimedia features is pushing device manufacturers to integrate more advanced peripherals such as multi-megapixel cameras and larger screens. Integrating these capabilities into next-generation devices brings new challenges to the industry in terms of power, time-to-market and overall system costs. To address these challenges, the Mobile Industry Processor Interface (MIPI ®) Alliance defines and promotes open interface specifications, such as the Camera Serial Interface (CSI-2), Display Serial Interface (DSI), which all use the MIPI D-PHY. As a leading provider of interface IP, Synopsys ’ high-quality, silicon-proven DesignWare D-PHY IP is available today in advanced process technologies.
Features : - Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro; Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
- Supports PHY Protocol Interface (PPI)
- Low-power escape modes and ultra low-power state modes
- Shutdown mode; SCAN and loopback BIST modes
- Extensive access to internal programmability registers
- Master, slave, Tx and Rx-only configurations; Attachable PLL for master applications
- Flexible input clock reference; 50% DDR output clock duty cycle
- Silicon-proven, robust design available in advanced process technologies
Categories :
Maturity : Available on request
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

Deliverables : - Databook
- Behavioral model
- LEF file
- .LIB file
- GDSII Layout Database

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