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 Synopsys 
Part Number : dwc_adc_highspeed_sar_fujitsu
Short Desc. : 12-bit, High Speed SAR ADC in Fujitsu (40nm)
Overview :
With more than 17 years of experience in developing analog IP solutions, Synopsys offers a comprehensive portfolio of more than 100 silicon-proven DesignWare ® Data Converter IP products consisting of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), auxiliary converters, video DACs (VDACs) and analog front-ends (AFEs). Synopsys ’ strong application expertise in areas such as mobile communications, cellular IoT, and wireless connectivity (i.e., LTE/LTE-A, NBIOT/CAT-M, WiFi.11ac/ax), wireline communications (i.e., PLC, G.hn, MoCA), IF demodulation, video, imaging and multimedia results in high-quality data converter IP tha t helps system-on-chip (SoC) designers meet their specific design requirements. The DesignWare Data Converter IP offers very high performance, high speed, ultra-low power dissipation, and small area, and supports a wide range of foundry process technologies ranging from 180-nm to 12-nm. Synopsys ’ high-quality DesignWare Data Converter IP solutions have been implemented in more than 300 SoCs, giving designers confidence that they can successfully integrate high-performance analog IP into their SoCs with less risk and improved time-to-results.
Features : - Over 17 years of delivering proven data conversion solutions
- Supporting all communication protocols, leveraging extensive application expertise
- Complete portfolio of silicon proven IP includes: – High-performance, high-speed 12-bit at 320 MSPS ADC and 12-bit at 640 MSPS DAC – General-purpose, high-resolution ADCs, auxiliary DACs and VDACs Compact design and ultra low-power dissipation
- High-quality IP and excellent support
- Robust, fully validated solutions
- Highly flexible solutions
Categories :
Maturity : Available on request
Portability :
Type :
 Hard IP 
Foundry :
Fujitsu
Nodes :
40nm
Process :
LP

Deliverables : - Databook
- Behavioral verilog model
- Abstract LEF and timing LIB files; CDL Netlist for LVS
- GDSII layout database
- Assembly guidelines and full integration support
Verific: SystemVerilog & VHDL Parsers
TrueCircuits:



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