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 Mixel, Inc. 
Part Number : MXL-DPHY-CSI2-TX+-T028HPCP-RF-ULL
Short Desc. : MIPI CSI-2 MASTER PHY IP
Overview :

The MXL-DPHY-CSI2-TX+ is a high-frequency low-power, source-synchronous, physical layer supporting the MIPI Alliance Specification for D-PHY v2.1, which is backward compatible with MIPI Specification for D-PHY v1.2. The PHY is configured as a MIPI master supporting Camera Serial interface CSI-2 v1.3. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.


Features : - Consists of 1 Clock lane and 4 Data lanes.
- Supports MIPI Alliance Specification for D-PHY Version 2.1
- Supports both high speed and low-power modes.
- 80 Mbps to 2.5 Gbps data rate in high speed mode.
- 10 Mbps data rate in low-power mode
- Low power dissipation.
- Testability support
Categories :
Tags : MIPI, MIPI CSI-2, MIPI D-PHY,
Maturity : Silicon Proven
Portability :
Type :
 Hard IP 
Foundry :
TSMC
Nodes :
28nm
Process :
HPC+

Deliverables : - Data Sheet
- GDSII Database & LEF
- LVS Netlist & Physical Verification Report
- RTL & Integration Guidelines
- One year support



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