Mixel, Inc. 
Part Number : MXL_DPHY_CSI2_TX_TW_110ISG
Short Desc. : MIPI D-PHY 4 Lane CSI2-TX 1.2G
Overview :

The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI master optimized for camera interface applications (CSI-2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.

Features : - Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI Standard 1.2 for D-PHY
- Supports both high speed and low-power modes
- 80 Mbps to 1.2Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Serializer included
- Low power dissipation
Categories :
Tags : MIPI CSI-2, MIPI D-PHY, 110 nm
Maturity : Silicon Proven
Portability :
Type :
 Hard IP 
Foundry :
Nodes :

Deliverables : - Datasheet
- GDSII and LVS Netlist
- Integration Guideline
- Timing Model and Behavioral Model
- Physical Verification Report
- One year support

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