Part Number : CCSDS_SCCC_Turbo_Encoder_Decoder
Short Desc. : CCSDS SCCC Turbo Encoder Decoder
Overview :

The recommended CCSDS 131.2-B-1 standard in-troduces a Serial Concatenated Convolutional Code(SCCC). Main goal of this code is to allow an efficient use of available bandwidth, by allowing to select from 27 valid configurations with a wide range of constellations, block lengths and code rates. The outstanding error correction performance of the SCCC code in combination with the high data rates makes this IP core the ideal fit for further applications where high throughput and high spectral efficiency is key for operation.

Features : - Compliant with CCSDS 131.2-B-1
- Support for all 27 ACM formats
- Support for all modulation schemes (QPSK, 8-PSK, 16-APSK, 32-APSK,64-APSK)
Categories :
Tags : CCSDS SCCC Turbo Decoder + Encoder
Portability :
Type : Soft
Deliverables : - VHDL source code or synthesized netlist
- HDL simulation models e.g. forAldec’s Riviera-PRO
- VHDL testbench
- Bit-accurate Matlab, C or C++simulation model
- Comprehensive documentation
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: DDR 4/3
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