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 TES Electronic Solutions GmbH 
Part Number : CDC 200 – Configurable Display Controller IP
Short Desc. : Fully Customizable Display Controller IP supporting the OpenWF display API specification
Overview :

Fully Customizable Display Controller IP supporting the OpenWF display API specification. A number of features can be configured at synthesis time and programmed at run time. The display controller can be applied to e.g. FPGA systems with a resource optimized, application specific feature configuration or to ASIC projects applying a more generic feature set and thus more flexibility.

 

The main functionality of CDC is reading images (layers) from memory, combining them on-the-fly e.g. by blending, cropping and windowing and generating a video output stream of the combined image.

On the output the controller provides a digital RGB signal with video data and signals for horizontal/vertical blank and synchronization. Optionally a digital component (YCBCR) output signal can be configured at synthesis time. The CDC’s output typically is then connected with the physical display output block like an HDMI our LVDS IP block or a Video DAC.


Features : - •High Resolutions
- Up to 64k x 64k pixels
- Maximum resolution can be constrained at synthesis time to save resources
- Programmable resolution needs external programmable PLL
- •Multiple Layers
- Number of layers and layer-specific features configurable at synthesis time
- Blending
- Layer blending
- colorResult = fn × colorn + fn-1 × colorn-1 ; n: layer position
- Blending technique configurable at synthesis time:
- Simplified algorithm (less gates/LEs)
- Precise algorithm (more gates/LEs)
- Blending modes for each layer, configurable at synthesis time
- Standard alpha blending
- Pre-multiplied alpha layers
- Additional constant alpha (fade in/out of layers)
- Per-pixel alpha can be stored in dedicated alpha layers (8 bit alpha)
- Configurable background layer for multi-color backgrounds (needs extra internal memory) or single
- programmable background color
- Windowing
- Blending only a programmable rectangular area of one layer into the other
- ‘Picture-in-Picture’ video overlay
- Multiple still images and videos on one display
- • CLUT (Color Look-Up Table) option for every layer
- Usage of indexed formats, e.g.
- 8 bit indexed
- 8 bit alpha + 8 bit indexed
- 4 bit alpha + 4 bit indexed
- Up to 256 24 bit color values in CLUT RAM
- •Color Keying
- Define transparent color for formats without alpha
- •Gamma Correction
- Adapt image output to display characteristics
- Brightness + contrast control
- Dithering
- Softer color transitions for displays with less color depth
- Flexible dithering: switched on and off during run-time
- Different implementations selectable (trade-off flexibility vs. resource usage)
- Ordered dithering
- Pseudo random dithering
- •Flexible Input Color Formats
- Up to 8 input formats selectable per layer
- Available input color formats :
- 32 bit ARGB8888
- 24 bit RGB888
- 16 bit RGB565
- 16 bit ARGB1555
- 16 bit ARGB4444
- 8 bit luminance, no alpha
- 8 bit alpha/luminance 44
- 16 bit alpha/luminance 88
- Available output color formats:
- RGB 888
- Internal pixel color format is ARGB8888
- • Parallel Pixel Output
- RGB888 (24 bit)
- Pixel clock, HSync, VSync, Data enable (polarity configurable)
- Serialization logic (e.g. OpenLDI, MIPI DSI) can easily be adapted
- •Dual-View and Dual-Port Modes
- Assign layers to two independent views/ports
- Support of special dual-view panels
- Support of dual-link modes
- •Slave Timing Mode
- Input synchronization to external video source timing instead of internal timing generator
- •Bus system
- Generic bus interface easily adaptable to any target bus system
- CDC currently supports AMBA APB and AHB/AXI4 as well as the IntelPSG (ex. Altera) Avalon bus interface.
Categories :
Tags : Display Controller
Maturity : Production Silicon
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria 10
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
ARRIA V GZ
ARRIA V ST
ARRIA V SX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
EP5C
FLEX 10K
HardCopy
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
HardCopy Stratix
MAX II
MAX V
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
STRATIX III E
Stratix IV
STRATIX IV E
STRATIX IV GT
STRATIX IV GX
Stratix V
STRATIX V E
STRATIX V GS
STRATIX V GT
STRATIX V GX
Lattice :
ispClock
ispMACH 4000
LatticeEC/ECP
LatticeECP2
LatticeECP2M
LatticeECP3
LatticeSC
LatticeSCM
LatticeXP
LatticeXP2
MachXO
MachXO2
Platform Manager
Power Manager II
Xilinx :
Artix-7
Kintex-7
Kintex-7 -2L
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type :
 Hard IP 
Foundry :
Common Platform
Dongbu
Fujitsu
GlobalFoundries
Huali
IBM
Intel Corporation
LFoundry
Renesas
Samsung
Silterra
SMIC
ST Microelectronics
TowerJazz
TSMC
UMC
X-Fab
Nodes :
7nm
8nm
10nm
11nm
12nm
14nm
16nm
20nm
22nm
28nm
32nm
40nm
45nm
55nm
65nm
80nm
90nm
110nm
130nm
140nm
150nm
152nm
160nm
180nm
250nm
350nm

Deliverables : - RTL Code in VHDL, Software Drivers, Documentation
call for Contribution



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