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 Digital Core Design 
Part Number : DSHA2-256
Short Desc. : SHA2-256 hash with HMAC mode
Overview :

Our latest DSHA2-256 IP Core is a universal solution which efficiently accelerates SHA2-256 hash with native HMAC mode. This IP targets authenticity and data integrity verification in digital signature protocols and all aspects of secured communication. It’s worth to mention that due to its unique features, the DSHA2-256 IP Core might also be used in crypto currency computations acceleration.


Features : - FIPS PUB 180-4 compliant SHA2-256 function
- RFC 2104 compliant HMAC mode native support
- SHA2 224 and 256 bit modes support
- Secure storage for precomputed HMAC keys
- Hash/HMAC context swapping
- Internal, automatic padding module
- Binary message resolution support
- Flexible data read/write modes
- AMBA AHB, AXI4, APB interface ready
- Software support:
- Software driver with OpenSSL/MbedTLS interface ready
- Applications
- Digital signature
- Data integrity
- Key derivation
- TLS/SSH/PGP IPsec communication
Categories :
Tags : SHA-3 Secure Hash Function Core SHA2
Maturity : 2019
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria 10
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
ARRIA V GZ
ARRIA V ST
ARRIA V SX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
EP5C
FLEX 10K
HardCopy
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
HardCopy Stratix
MAX II
MAX V
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
STRATIX III E
Stratix IV
STRATIX IV E
STRATIX IV GT
STRATIX IV GX
Stratix V
STRATIX V E
STRATIX V GS
STRATIX V GT
STRATIX V GX
Lattice :
ispClock
ispMACH 4000
LatticeEC/ECP
LatticeECP2
LatticeECP2M
LatticeECP3
LatticeSC
LatticeSCM
LatticeXP
LatticeXP2
MachXO
MachXO2
Platform Manager
Power Manager II
Xilinx :
Artix-7
Kintex-7
Kintex-7 -2L
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type : Soft
Deliverables : - The list of deliverables consists of:

- Source code:
- VERILOG Source Code
- Software driver in C with OpenSSL/MbedTLS interface ready
- VERILOG test bench environment
- Active-HDL automatic simulation macros
- ModelSim automatic simulation macros
- Tests with reference responses
- Technical documentation
- HDL core specification
- Software driver documentation
- Synthesis scripts
- Example application
- Technical support
- IP Core implementation support
- 3 months of maintenance
- Delivery the IP Core updates, minor and major versions changes
- Delivery the documentation updates



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