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 Mixel, Inc. 
Part Number : MXL-DPHY-v2.5-UNIV-T-022ULP
Short Desc. : MIPI Universal D-PHY IP - 4.5Gbps/lane, MIPI D-PHY v2.5 Compliant
Overview :

The MXL-D-PHY-UNIV-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5. The PHY can be configured as a MIPI Master or MIPI Slave supporting camera interface CSI-2 and display interface DSI/DSI-2 applications.

Mixel D-PHY v2.5 supports speeds up to 4.5Gbps per lane, an aggregate data rate of 18Gbps. It supports all v2.5 features not available in previous versions of the specifications such as Spread Spectrum Clocking (SSC) and transmit equalization (de-emphasis). It also supports new power saving functionality such as HS-TX half swing mode and the HS-RX unterminated mode. The new Alternate LP Mode, suitable for IoT applications with long channels, is also supported, enabling Fast Bus Turnaround.


Features : - Supports MIPI Alliance Specification for D-PHY Version 2.5
- Backward compatible with MIPI Specifications for D-PHY v2.1, v1.2, and v1.1
- Consists of 1 Clock lane and 4 Data lanes
- Embedded high performance, highly programmable, PLL
- PLL supports SSC mode, Fractional mode, and Integer mode
- Supports both high speed and low-power modes
- Up to 4.5 Gbps data rate per lane with Deskew calibration
- Supports High Speed TX De-emphasis Equalization
- Supports High Speed RX CTLE
- 10 Mbps data rate in low-power mode
- Low power dissipation
- Testability support including internal loopback
- Calibrator for resistance termination
Categories :
Tags : MIPI, D-PHY, DPHY, PHY, Mixel, CSI, CSI-2, dsi, dsi-2
Maturity : Upon request
Portability :
Type : Soft
Deliverables : - Datasheet
- GDSII and LVS Netlist
- Integration Guideline
- Timing Model and Behavioral Model
- RTL
- One year support



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