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Part Number : GNSS Digital IP
Short Desc. : Multi-constellation GNSS IP supporting GPS, GALILEO, GLONASS, BeiDou3, QZSS, IRNSS, SBAS.
Overview :

Multi-frequency, multi-constellation GNSS IP for ultra low power, high sensitivity and high accuracy GNSS receiver integration into SoC

This comprehensive future proof Global GNSS IP is extracted from a 5th generation production chip, it is all-in view, multi-frequency and multi-constellation GNSS baseband IP core for integration into SoCs from low power IoT to Automotive Precision Navigation.

The feature rich, low power. Low gate count baseband provides ultra-fast acquisition and precision tracking performance achieving a small gate count.

It supports processing two RF channels simultaneously providing dual frequency GNSS capability, along with superior immunity features against pulsed and multi-tone interference.

The IP core is highly SW configurable to support any of the legacy, modernized and potential future GNSS signals of all available constellations, concurrently or sequentially based on the need of the application.

We can also customize and optimize the IP to meet your specific requirements if required.


Features : - Supports multi band signals - L1, L2, L5 and S band frequencies
- Multi-constellation support GPS, GALILEO, GLONASS, BeiDou, QZSS, IRNSS, and SBAS.
- Efficient and generic PRN code handling architecture to support future signal structures
- Massive and wide bandwidth correlators enable fast acquisition and high precision
- Multi-tone continuous wave interference mitigation and pulsed interference mitigation to enable receiver to operate in intentional or unintentional interference environment
- Processes ADC output from one or two RF front- ends
- Configurable ADC interface:
- o SDR (sampled data on rising edge)
- o DDR (sampled data on rising and falling)
- o various sampling frequencies
- o real or complex samples
- o 1-bit to 5-bit ADC data processing
- Enables PPP and RTK positioning
- Measurement generation on external event or internal 1PPS event
- Up to 1KHz measurement rate
- Battery Backed Counter to maintain GNSS Time
- AMBA compliant AHB or Synchronous Parallel Bus interface to CPU
- Patented architecture for lowest power and lower logic area
Categories :
Tags : Multi-constellation GNSS IP supporting GPS, GALILEO, GLONASS, BeiDou3, QZSS, IRNSS, SBAS.
Maturity : 5th Generation Production Chipset Design
Portability :
Type : Soft
Deliverables : - Fully synthesizable and technology independent RTL in VHDL
- Compatible executable binary file
- Synthesis scripts along with timing constraints
- Verification environment including the test benches, input and expected output files
- RTL IP integration manual
- FPGA/ASIC evaluation platform for testing the performance
Verific: SystemVerilog & VHDL Parsers



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